System and method for the design of digital hardware

1. A computer-implemented system for facilitating the design of a digital circuit which comprises a plurality of logical constructs, wherein the system is configured such that each time each logical construct is executed during a software simulation pass it is associated with a unique tag, wherein each tag is configured to correspond to a physical aspect of a hardware representation of the design,

wherein the logical construct is:

a clock signal;

a reset signal;

a register;

a memory block;

a wire, wherein a wire is a mechanism which enables a signal to be read before it is written;

a tri-state signal;

a module instantiation with an associated name;

a module input signal;

a module output signal;

a module tri-state input and output signal;

a sensitivity list; and/or

a debugging element.

2. The system according to claim 1 , wherein:

the simulation is performed by repeated execution passes through code which implements the design; and/or

the same tags are associated with corresponding executions of the logical constructs during different simulation passes.

3. The system according to claim 1 , wherein the system is further configured to ensure that the tagged logical constructs can only occur within portions of code which are not conditional upon the state of any input signal.

4. The system according to claim 1 , wherein the system comprises:

a simulation component;

a synthesis component;

a specification for a hardware description language (HDL);

a set of syntactic and semantic rules for an HDL;

a simulation software library; and/or

a synthesis conversion tool.

5. The system according to claim 1 , wherein the system is arranged to maintain information relating to the status of a simulation of the design.

6. The system according to claim 1 , wherein the system is configured to generate at least one simulator object arranged to maintain data relating to a simulation of the design.

7. The system according to claim 6 , wherein the system is further configured to generate a sole manager object, wherein the manager object has access to, and/or is in communication with, the at least one simulator object.

8. The system according to claim 1 , wherein the system is configured to:

i) facilitate the design of the digital circuit using a programming language;

optionally wherein the programming language is C++, a C-type language or an object-oriented language;

ii) convert a design written in the programming language to a hardware design;

iii) create a representation of the digital circuit in a programming language

iv) compile or synthesize the design of the digital circuit into a hardware design;

v) use, represent and/or manipulate an RTL abstraction of the digital circuit; and/or

vi) determine when a steady-state has been reached and that the circuit is stable during a simulation.

9. The system according to claim 1 , wherein the system is configured such that:

a simulator object is able to store and/or maintain simulation state by retrieving it from a sole manager object;

a logical construct object is able to retrieve its initial state from the simulator object on construction and save its state on destruction; and

logical constructs can only occur within portions of code which are not conditional upon the state of any input signal.

10. A computer-implemented method for facilitating the design of a digital circuit which comprises a plurality of logical constructs, wherein the method comprises:

assigning a unique tag to each logical construct, the same tag being assigned to the same logical construct each time the logical construct is executed during a software simulation pass,

wherein each tag is configured to correspond to a physical aspect of a hardware representation of the design,

wherein the logical construct is:

a clock signal;

a reset signal;

a register;

a memory block;

a wire, wherein a wire is a mechanism which enables a signal to be read before it is written;

a tri-state signal;

a module instantiation with an associated name;

a module input signal;

a module output signal;

a module tri-state input and output signal;

a sensitivity list; and/or

a debugging element.

11. The method according to claim 10 , wherein the method comprises:

simulating the design by repeatedly performing execution passes through code which implements the design; and/or

associating the same tags with corresponding executions of the logical constructs during different simulation passes.

12. The method according to claim 10 , wherein the method comprises ensuring that the tagged logical constructs can only occur within portions of code which are not conditional upon the state of any input signal.

13. The method according to claim 10 , wherein the method comprises the use of:

a simulation component;

a synthesis component;

a specification for a hardware description language (HDL);

a set of syntactic and semantic rules for an HDL;

a simulation software library; and/or

a synthesis conversion tool.

14. The method according to claim 10 , further comprising maintaining information relating to the status of a simulation of the design.

15. The method according to claim 10 , further comprising generating at least one simulator object arranged to maintain data relating to a simulation of the design.

16. The method according to claim 15 , further comprising generating a sole manager object, wherein the manager object has access to, and/or is in communication with, the at least one simulator object.

17. The method according to claim 10 , wherein the method comprises at least one of:

i) using a programming language to facilitate the design of the digital circuit;

optionally wherein the programming language is C++, a C-type language or an object-oriented language;

ii) converting a design written in the programming language to a hardware design;

iii) creating a representation of the digital circuit in a programming language

iv) compiling or synthesizing the design of the digital circuit into a hardware design;

v) using, representing and/or manipulating an RTL abstraction of the digital circuit; and

vi) determining when a steady-state has been reached and that the circuit is stable during a simulation.

18. The method according to claim 10 , wherein the method comprises:

enabling a simulator object to store and/or maintain simulation state by retrieving it from a sole manager object;

enabling a logical construct object to retrieve its initial state from the simulator object on construction and save its state to the simulator object on destruction; and

ensuring that logical constructs can only occur within portions of code which are not conditional upon the state of any input signal.

19. A computer-implemented system for simulating and/or synthesizing the design of a digital circuit which comprises a plurality of logical constructs, wherein the system is configured such that:

a simulator object is able to store and/or maintain simulation state by retrieving it from a sole manager object;

a logical construct object is able to retrieve its initial state from the simulator object on construction and save its state on destruction; and

logical constructs can only occur within portions of code which are not conditional upon the state of any input signal.

20. A computer-implemented method for simulating and/or synthesizing the design of a digital circuit which comprises a plurality of logical constructs, comprising:

enabling a simulator object to store and/or maintain simulation state by retrieving it from a sole manager object;

enabling a logical construct object to retrieve its initial state from the simulator object on construction and save its state to the simulator object on destruction; and

ensuring that logical constructs can only occur within portions of code which are not conditional upon the state of any input signal.