Logic integrated circuit and semiconductor device

1. A logic integrated circuit comprising:

a three-terminal resistance change switch including a first resistance change switch and a second resistance change switch being connected in series;

a reading circuit which reads first data based on a resistance state of the first resistance change switch and second data based on a resistance state of the second resistance change switch, each of the first data and the second data includes 0 or 1; and

a first error detection circuit which compares the first data with the second data and issue an output based on a result of the comparison.

2. The logic integrated circuit according to claim 1 , wherein, when the first data and the second data are different, the first error detection circuit determines that there is an error.

3. The logic integrated circuit according to claim 1 , further comprising:

a switch cell array including a plurality of the three-terminal resistance change switches; and

a selection circuit which selects any one of the three-terminal resistance change switches in the switch cell array.

4. The logic integrated circuit according to claim 3 , wherein the switch cell array includes

a group of N (N is an integer not less than 2) first wirings extending in a column direction,

a group of M (M is an integer not less than 2) second wirings extending in a row direction, and

the three-terminal resistance change switches each provided at an intersection between the first wiring and the second wiring and configured to switch connection and non-connection between the first wiring and the second wiring.

5. The logic integrated circuit according to claim 4 , further comprising a second error detector that determines that,

when a number of 1 in the first data and the second data of the three-terminal resistance change switches on the second wiring is smaller than a predetermined number L (L is a positive integral multiple of 2), 0 in the first data and the second data of the three-terminal resistance change switch in which an error is determined by the first error detection circuit is an error, and determine that,

when a number of 1 is larger than the predetermined number L, 1 in the first data and the second data of the three-terminal resistance change switch in which an error is determined by the first error detection circuit is an error.

6. The logic integrated circuit according to claim 5 , further comprising a writing circuit that inverts 0 determined to be an error by the second error detector into 1, or inverts 1 determined to be an error by the second error detector into 0.

7. A semiconductor device comprising the logic integrated circuit according to claim 1 .

8. A logic integrated circuit comprising:

a three-terminal resistance change switch including a first resistance change switch and a second resistance change switch being connected in series;

a reading circuit which reads a first data based on a resistance state of the first resistance change switch and second data based on a resistance state of the second resistance change switch; and

a first error detection circuit which compares the first data with the second data and issue and output based on a result of the comparison, wherein

the three-terminal resistance change switch includes a common terminal for connecting the first resistance change switch and the second resistance change switch in series,

each of the first resistance change switch and the second resistance change switch has a bipolar type, and

the first resistance change switch and the second resistance change switch have polarities symmetrical with respect to the common terminal.

9. The logic integrated circuit according to claim 8 , further comprising a cell transistor, a bit line, and a row selection line, wherein

the common terminal is connected to the bit line through the cell transistor, and

a gate of the cell transistor is connected to the row selection line.

10. The logic integrated circuit according to claim 9 , further comprising a first transistor, a second transistor, a third transistor, a wiring PV, a wiring PH, a wiring PB, and a column selection line, wherein

the first wiring is connected to the wiring PV through the first transistor,

a gate of the first transistor is connected to the column selection line,

the second wiring is connected to the wiring PH through the second transistor,

a gate of the second transistor is connected to the row selection line,

the bit line is connected to the wiring PB through the third transistor, and

a gate of the third transistor is connected to the column selection line.

11. The logic integrated circuit according to claim 10 , further comprising a column selection circuit, and a row selection circuit, wherein

the column selection circuit uses the column selection line to render the first transistor conductive, and thereby connect the wiring PV and the first wiring to each other,

the row selection circuit uses the row selection line to render the second transistor conductive, and thereby connect the wiring PH and the second wiring to each other, and

the column selection circuit uses the column selection line to render the third transistor conductive, and thereby connect the wiring PB and the bit line to each other.

12. The logic integrated circuit according to claim 8 , wherein

the first resistance change switch includes a first terminal, a first resistance change element, and the common terminal,

the second resistance change switch includes a second terminal, a second resistance change element, and the common terminal,

the first resistance change element includes a series connection among a first electrode connected to the first terminal, a first resistance change layer, and a second electrode connected to the common terminal,

the second resistance change element includes a series connection among a third electrode connected to the second terminal, a second resistance change layer, and a fourth electrode connected to the common terminal, and

the first electrode and the third electrode each include an active electrode, and the second electrode and the fourth electrode each include an inactive electrode, or the first electrode and the third electrode each include an inactive electrode, and the second electrode and the fourth electrode each include an active electrode.

13. The logic integrated circuit according to claim 12 , wherein each of the first resistance change element and the second resistance change element has a metal bridge type.

14. The logic integrated circuit according to claim 12 , wherein each of the first resistance change layer and the second resistance change layer includes an ion conductor.