Superconducting bump bonds
A device ( 100 ) includes a first chip ( 104 ) having a first circuit element ( 112 ), a first interconnect pad ( 116 ) in electrical contact ( 118 ) with the first circuit element, and a barrier layer ( 120 ) on the first interconnect pad, a superconducting bump bond ( 106 ) on the barrier layer, and a second chip ( 102 ) joined to the first chip by the superconducting bump bond, the second chip having a quantum circuit element ( 108 ), in which the superconducting bump bond provides an electrical connection between the first circuit element and the quantum circuit element.
1. A method comprising:
providing a first chip comprising a first circuit element;
forming a first aluminum interconnect pad on a first surface of the first chip so that the first aluminum interconnect pad is electrically connected to the first circuit element;
forming a first titanium nitride barrier layer on the first aluminum interconnect pad;
providing a second chip comprising a second circuit element;
forming an indium bump bond; and
joining the first chip to the second chip with the indium bump bond so that the first circuit element is electrically connected to the second circuit element, wherein joining the first chip to the second chip is performed at room temperature.
2. The method of claim 1 , wherein room temperature is between approximately 18° C. and approximately 30° C.
3. The method of claim 2 , further comprising removing a native oxide from the first aluminum interconnect pad prior to forming the first titanium nitride barrier layer.
4. The method of claim 3 , wherein removing the native oxide comprises ion milling a surface of the first aluminum interconnect pad.
5. The method of claim 2 , wherein forming the first titanium nitride barrier comprises reactive sputtering titanium nitride on the first aluminum interconnect pad.
6. The method of claim 2 , further comprising ion milling a surface of the first titanium nitride barrier layer prior to joining the first chip to the second chip.
7. The method of claim 2 , further comprising exposing a surface of the indium bump bond to a H 2 plasma.
8. The method of claim 2 , further comprising:
forming a second aluminum interconnect pad on a first surface of the second chip so that the second aluminum interconnect pad is electrically connected to the second circuit element; and
forming a second titanium nitride barrier layer on the second aluminum interconnect pad of the second chip.
9. The method of claim 8 , further comprising removing a native oxide from the second aluminum interconnect pad of the second chip prior to forming the second titanium nitride barrier layer.
10. The method of claim 9 , wherein removing the native oxide from the second aluminum interconnect pad comprises ion milling a surface of the second aluminum interconnect pad.
11. The method of claim 8 , wherein forming the second titanium nitride barrier layer on the second aluminum interconnect pad comprises reactive sputtering titanium nitride on the second aluminum interconnect pad.
12. The method of claim 8 , further comprising ion milling a surface of the second titanium nitride barrier layer prior to joining the first chip to the second chip.
13. The method of claim 8 , wherein forming the indium bump bond comprises depositing indium on the first titanium nitride barrier, on the second titanium nitride barrier, or on both the first and second titanium nitride barriers.
14. The method of claim 2 , wherein the first circuit element comprises a rapid single flux quantum (RSFQ) device and the second circuit element comprises a quantum circuit element.