High-voltage digital power amplifier with sinusoidal output for RFID
A digital power amplifier comprises: an integrated circuit (IC2); an adaption circuit of discrete components connected to first and second transmission output pins of an integrated circuit to adapt the output signal and feed a substantial sinusoidal output current with a transmission resonance frequency to an RFID antenna. IC2 comprises a digital control section with N wave-forming contacts to output a digital wave-forming bit combination of N bits with a clock frequency M-times the transmission resonance frequency; N driver blocks each connected with a first contact to one of the wave-forming contacts and N/2 of them connected with a second contact to the first transmission output pin and the other N/2 of them connected with their second contact to the second transmission output pin. The driver blocks provide increments of the substantial sinusoidal output current to the first and second transmission output pins.
1. A digital power amplifier for driving a radio frequency identification (RFID) antenna with a substantial sinusoidal output current, wherein the digital power amplifier comprises:
an integrated circuit including a first transmission output pin and a second transmission output pin, the integrated circuit configured to provide an output signal between the first transmission output pin and the second transmission output pin; and
an adaption circuit configured to adapt the output signal and feed the substantial sinusoidal output current with a transmission resonance frequency to the RFID antenna, wherein the integrated circuit comprises:
a digital control section including a number N of wave-forming contacts, each wave-forming contact providing a voltage, the digital control section configured to output a digital wave-forming bit combination of N bits with a clock frequency that is a number M-times the transmission resonance frequency, wherein N and M are integers and N is an even number greater than or equal to 2; and
N driver blocks each having a first contact and a second contact, the first contact connected only to one of the wave-forming contacts and N/2 of the N driver blocks connected with a respective second contact only to the first transmission output pin and the other N/2 of the N driver blocks connected with another respective second contact only to the second transmission output pin, wherein the N driver blocks are built to provide increments of the substantial sinusoidal output current to the first and second transmission output pins and wherein each of the N/2 driver blocks connected to the first transmission output pin is built identical and each of the other N/2 driver blocks connected to the second transmission output pin is built identical.
2. The digital power amplifier according to claim 1 , wherein each of the N driver blocks includes a level shifter, the first contact of the driver block arranged to supply the voltage provided by the wave-forming contact to the level shifter, the level shifter configured to shift the voltage provided at the wave-forming contact to a higher voltage.
3. The digital power amplifier according to claim 2 , wherein each of the respective second contacts of the other N/2 of the N driver blocks is connected to the second transmission output pin and each of the other N/2 of the N driver blocks includes an inverter, the inverter configured to invert the potential of the voltage provided by the level shifter.
4. The digital power amplifier according to claim 3 , wherein each of the N driver blocks includes a series capacitor arranged between the inverter and the second contact of the driver block and fed by either the shifted voltage of the level shifter or an inverted voltage of the level shifter.
5. The digital power amplifier according to claim 4 , wherein the integrated circuit is implemented in CMOS technology and wherein the series capacitors are Metal-Oxide-Metal capacitors that use the capacitive effect of connecting lines within the integrated circuit.
6. The digital power amplifier according to claim 1 , wherein the adaption circuit comprises two resonance capacitors each having a first contact to the first transmission output pin or the second transmission output pin and a second contact connected to a ground pin.
7. The digital power amplifier according to claim 1 , wherein the transmission resonance frequency of the RFID antenna is 13.56 MHz and the clock frequency is a multiple of the transmission resonance frequency and in particular 8-times, 16-times, 32-times or 64-times the transmission resonance frequency.
8. The digital power amplifier according to claim 1 , wherein the digital control section stores M digital wave-forming bit combinations in a table for each of data bits “ 0 ” and “ 1 ” and wherein the digital control section is built to output the M digital wave-forming bit combinations of either data bit “ 0 ” or “ 1 ” at the N wave-forming contacts to transform data bits of “ 0 ” or “ 1 ” into the substantial sinusoidal output current.