IP Library › Granted Patent US 10,580,108
Granted Patent B2
US 10,580,108 · App. 16/062,511 · Granted Mar 3, 2020

Method and apparatus for best effort quality of service (QoS) scheduling in a graphics processing architecture

Inventors: Yao Zu Dong (Shanghai, CN); Kun Tian (Shanghai, CN); Tian Zhang (Shanghai, CN); Yulei Zhang (Shanghai, CN)
Assignee: Intel Corporation
G06T1/20G06F9/4887
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,580,108
App. No.
16/062,511
Granted
Mar 3, 2020
Kind
B2
Abstract

An apparatus and method for best effort quality of service scheduling in a graphics processing architecture. For example, one embodiment of an apparatus comprises: a graphics processing unit (GPU) to perform graphics processing operations for a plurality of guests; a plurality of buffers to store one or more graphics commands associated with each guest to be executed by the GPU; and a scheduler to evaluate commands in the buffers of a first guest to estimate a cost of executing the commands, the scheduler to select all or a subset of the buffers of the first guest for execution on the GPU based on a determination that the selected buffers can be executed by the GPU within a remaining time slice allocated to the first guest.

Claims (25)

1. An apparatus comprising:

a graphics processing unit (GPU) to perform graphics processing operations for a plurality of guests;

a plurality of buffers to store one or more graphics commands associated with each guest to be executed by the GPU; and

a scheduler to evaluate commands in the buffers of a first guest to estimate a cost of executing the commands, the scheduler to select all or a subset of the buffers of the first guest for execution on the GPU based on a determination, utilizing a margin threshold value, that the selected buffers can be executed by the GPU within a remaining time slice allocated to the first guest.

2. The apparatus as in claim 1 wherein the scheduler is to estimate the cost of executing the commands based on data related to the commands and collected during prior execution of the commands.

3. The apparatus as in claim 1 wherein the scheduler is to choose a number of buffers which can be executed within a difference between the remaining slice time and the margin threshold value.

4. The apparatus as in claim 1 wherein the scheduler is to estimate the cost of executing the commands based on an accumulated cost of each commands and/or analysis of parameter of the commands.

5. The apparatus as in claim 1 wherein the scheduler is to estimate the cost of executing the commands using a rough estimate of the execution cost based on the number of buffers to be executed.

6. The apparatus as in claim 1 wherein the scheduler is to estimate the cost of executing the commands based on an execution time of certain types of commands having an associated cost above a threshold.

7. The apparatus as in claim 1 wherein the buffers comprise ring buffers.

8. The apparatus as in claim 7 wherein the ring buffers are arranged into a plurality of levels, and wherein the scheduler is configured to select all or the subset of the ring buffers of the first guest for execution on the GPU from a designated ring buffer level.

9. The apparatus as in claim 8 wherein the scheduler is configured to implement a temporary co-delivering policy to deliver commands from multiple ring buffers upon detecting interdependencies between the commands in the ring buffers.

10. The apparatus as in claim 9 wherein the interdependences comprise semaphores.

11. A method comprising:

performing graphics processing operations on a graphics processor unit (GPU) for a plurality of guests;

storing one or more graphics commands in a plurality of buffers associated with each guest to be executed by the GPU; and

evaluating commands in the buffers of a first guest to estimate a cost of executing the commands; and

selecting all or a subset of the buffers of the first guest for execution on the GPU based on a determination, utilizing a margin threshold value, that the selected buffers can be executed by the GPU within a remaining time slice allocated to the first guest.

12. The method as in claim 11 wherein estimating the cost of executing the commands is based on data related to the commands and collected during prior execution of the commands.

13. The method as in claim 11 wherein the number of buffers which can be executed is selected within a difference between the remaining slice time and the margin threshold value.

14. The method as in claim 11 wherein the cost of executing the commands is estimated based on an accumulated cost of each commands and/or analysis of the parameter of the commands.

15. The method as in claim 11 wherein the cost of executing the commands is estimated using a rough estimate of the execution cost based on the number of buffers to be executed.

16. The method as in claim 11 wherein the cost of executing the commands is estimated based on an execution time of certain types of commands having an associated cost above a threshold.

17. The method as in claim 11 wherein the buffers comprise ring buffers.

18. The method as in claim 17 wherein the ring buffers are arranged into a plurality of levels, and wherein all or the subset of the ring buffers of the first guest for execution on the GPU is selected from a designated ring buffer level.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2019
From: DONG, YAO ZU; TIAN, KUN; ZHANG, TIAN; ZHANG, YULEI
To: INTEL CORPORATION
Reel/Frame 050247/0488 →
Continuity (1)
Related Publication 20180374187A1 · Dec 27, 2018