Array substrate, display panel and display device
An array substrate, a display panel and a display device are disclosed. The array substrate includes a first data line and a second data line which extend substantially along a first direction and are adjacent to each other, a first gate line and a second gate line that extend substantially along a second direction intersected with the first direction and are adjacent to each other, and at least two sub-pixels which are sequentially arranged in parallel along the first direction; the first gate line and the second gate line are disposed at two sides of the at least two sub-pixels in the first direction, respectively.
1. An array substrate, comprising a pixel unit, wherein the pixel unit comprises:
a first data line and a second data line that extend substantially along a first direction;
a first gate line and a second gate line that extend substantially along a second direction, wherein the second direction is intersected with the first direction; and
three sub-pixels are sequentially arranged in parallel along the first direction;
wherein the three sub-pixels comprise a first sub-pixel adjacent to the first gate line, a third sub-pixel adjacent to the second gate line, and a second sub-pixel located between the first sub-pixel and the second sub-pixel,
the first sub-pixel is electrically connected to the first gate line and the first data line,
the third sub-pixel is electrically connected to the second gate line and the first data line, and
the second sub-pixel is electrically connected to the first gate line and the second data line, or is electrically connected to the second gate line and the second data line.
2. The array substrate according to claim 1 , wherein each of the sub-pixels comprises a thin film transistor (TFT) connected to one of the first data line and the second data line, and to one of the first gate line and the second gate line, which are configured to drive the each of the sub-pixels.
3. The array substrate according to claim 1 , wherein the three sub-pixels are disposed between the first data line and the second data line in the second direction.
4. The array substrate according to claim 1 , wherein the pixel unit is repeatedly arranged in the first direction and the second direction.
5. The array substrate according to claim 4 , wherein two pixel units that are adjacent in the second direction and are located at two sides of one second data line share the one second data line.
6. The array substrate according to claim 1 , wherein the three sub-pixels are a red sub-pixel unit, a green sub-pixel unit and a blue sub-pixel unit.
7. The array substrate according to claim 1 , wherein the second direction is perpendicular to the first direction.
8. The array substrate according to claim 7 , wherein
each of the sub-pixels comprises a driving electrode, and the driving electrode comprises:
a plurality of first driving sub-electrodes which extend along the second direction and are arranged to be spaced apart from each other along the first direction; and
at least one second driving sub-electrode which extends along the first direction and is configured to electrically connect the plurality of first driving sub-electrodes;
at least part of the second driving sub-electrode is further configured to form an electric field with at least one of the first data line and the second data line, the electric field being parallel to a rubbing alignment direction, and the rubbing alignment direction being parallel to the second direction.
9. The array substrate according to claim 8 , wherein
the first driving sub-electrode comprises a first electrode portion and a second electrode portion which extend along different directions, and
the first electrode portion and the second electrode portion are intersected with the rubbing alignment direction.
10. The array substrate according to claim 9 , wherein a portion of the at least one of the first gate line and the second gate line corresponding to the first electrode portion is parallel to the first electrode portion, and a portion of the at least one of the first gate line and the second gate line corresponding to the second electrode portion is parallel to the second electrode portion.
11. The array substrate according to claim 9 , further comprising a common electrode line, wherein the common electrode line is non-transparent and is disposed between adjacent two of the sub-pixels.
12. The array substrate according to claim 11 , wherein a portion of the common electrode line corresponding to the first electrode portion is parallel to the first electrode portion, and a portion of the common electrode line corresponding to the second electrode portion is parallel to the second electrode portion.
13. A display panel, comprising the array substrate according to claim 1 .
14. A display device, comprising the array substrate according to claim 1 .