High-speed low-power-consumption trigger
A high-speed low-power-consumption trigger, which comprises a control signal generation circuit, an enabling unit, and a latch structure. The latch structure comprises two input ends, two output ends, two enabling ends, a second enabling end, and a ground end. The enabling unit comprises two enabling circuits. An output signal X of the control signal generation circuit and an external control signal D serve as input signals of the first enabling circuit. An output end of the first enabling circuit is connected to the first enabling end. The output signal X of the control signal generation circuit and a phase-inverted signal DB of the external control signal D serve as input signals of the second enabling circuit. An output end of the second enabling circuit is connected to the second enabling end.
1. A high-speed low-power-consumption trigger, comprising a control signal generation circuit, an enabling unit, and a latch structure, wherein the latch structure comprises a first input end, a second input end, a first output end, a second output end, a first enabling end, a second enabling end, and a ground end, the enabling unit comprises a first enabling circuit and a second enabling circuit, an output signal X of the control signal generation circuit and an external control signal D serve as input signals of the first enabling circuit, an output end of the first enabling circuit is connected to the first enabling end, the output signal X of the control signal generation circuit and a phase-inverted signal DB of the external control signal D serve as input signals of the second enabling circuit, and an output end of the second enabling circuit is connected to the second enabling end; and the external control signal D serves as an input signal of the first input end, and the phase-inverted signal DB of the external control signal D serves as an input signal of the second input end.
2. The high-speed low-power-consumption trigger as in claim 1 , wherein the control signal generation circuit is a phase inverter, an input signal of the phase inverter is a clock signal CLK, and an output signal of the phase inverter is X.
3. The high-speed low-power-consumption trigger as in claim 2 , wherein the phase inverter comprises an NMOS transistor M 132 and a PMOS transistor M 22 , a source electrode of the PMOS transistor M 22 is connected to a power source, a drain electrode of the PMOS transistor M 22 is connected to a drain electrode of the NMOS transistor M 132 , a source electrode of the NMOS transistor M 132 is grounded, a gate electrode of the NMOS transistor M 132 is connected to a gate electrode of the PMOS transistor M 22 and is connected to the clock signal CLK, and the drain electrode of the NMOS transistor M 132 and electrodes of the PMOS transistor M 22 serve as output ends of the control signal generation circuit and generate the output signal X.
4. The high-speed low-power-consumption trigger as in claim 3 , wherein the latch structure comprises NMOS transistors M 32 to M 72 and PMOS transistors M 82 to M 122 , a source electrode of the PMOS transistor M 102 and a source electrode of the PMOS transistor M 112 are connected to the power source, a drain electrode of the PMOS transistor M 102 is connected to a source electrode of the PMOS transistor M 82 and a source electrode of the PMOS transistor M 122 respectively, a drain electrode of the PMOS transistor M 112 is connected to a source electrode of a PMOS transistor M 192 and a drain electrode of the PMOS transistor M 122 respectively, a gate electrode of the PMOS transistor M 122 is grounded; a drain electrode of the PMOS transistor M 82 is connected to a drain electrode of the NMOS transistor M 52 , a drain electrode of the NMOS transistor M 42 , a gate electrode of the PMOS transistor M 92 , and a gate electrode of the NMOS transistor M 62 respectively; a drain electrode of the PMOS transistor M 92 is connected to a drain electrode of the NMOS transistor M 62 , a drain electrode of the NMOS transistor M 72 , a gate electrode of the PMOS transistor M 82 , and a gate electrode of the NMOS transistor M 52 respectively; a gate electrode of the NMOS transistor M 42 serves as the first enabling end, a gate electrode of the NMOS transistor M 72 serves as the second enabling end, a source electrode of the NMOS transistor M 42 and a source electrode of the NMOS transistor M 72 are connected to a drain electrode of the NMOS transistor M 32 respectively, a source electrode of the NMOS transistor M 32 is grounded, and a gate electrode of the NMOS transistor M 32 is connected to the clock signal CLK; the drain electrode of the NMOS transistor M 52 and the drain electrode of the NMOS transistor M 62 are grounded; and the drain electrode of the NMOS transistor M 42 serves as the first output end of the trigger and generates an output signal QB, and the drain electrode of the NMOS transistor M 72 serves as the second output end of the trigger and generates an output signal Q.
5. The high-speed low-power-consumption trigger as in claim 4 , wherein the first enabling circuit comprises an AND gate AND 1 , an output end of the AND gate AND 1 is connected to the gate electrode of the NMOS transistor M 42 , the second enabling circuit comprises an AND gate AND 2 , and an output end of the AND gate AND 2 is connected to the gate electrode of the NMOS transistor M 72 .