IP Library › Granted Patent US 10,860,771
Granted Patent B2
US 10,860,771 · App. 16/076,304 · Granted Dec 8, 2020

Side channel aware automatic place and route

Inventors: Subbayya Chowdary Yanamadala (Dallas, TX); Daniel F. Yannette (Satellite Beach, FL); Brent Arnold Myers (Palm Beach, FL)
Assignee: CHAOLOGIX, INC.
G06F30/394G05F1/59G06F21/755G06F30/327G06F30/392G06F30/30G06F2119/06
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Quick Facts
Patent No.
US 10,860,771
App. No.
16/076,304
Granted
Dec 8, 2020
Kind
B2
Abstract

A power planning phase module, a placement phase module, and a routing phase module are provided that can replace, supplement, or enhance existing electronic design automation (EDA) software tools. The power planning phase module adds distributed power sources and a network of switching elements to the power frame or ring assigned to regions of a chip (that may be identified during a floor planning stage). The placement phase module optimizes a number and type of cells attached to each power source of the distributed power sources already added or to be added during the power planning phase. The routing phase module optimizes routing length to, for example, mask power consumption.

Claims (15)

1. A computer readable storage medium having instructions stored thereon for an electronic design automation tool that when executed by a processing system, direct the processing system to:

add charge storage elements and switching elements to a power frame;

identify an attach ratio for one or more types of standard cells, wherein the attach ratio is a number of standard cells attached to a charge storage element and is based at least on types of gates of the standard cells;

place the standard cells in groupings to attach to corresponding charge storage elements according to the attach ratio; and

vary routing length of connections between the standard cells and the charge storage elements of each grouping to optimize data leakage through power signature,

wherein the instructions to identify the attach ratio and place the standard cells in groupings direct the processing system to:

minimize clusters of a same gate type in a grouping.

2. The medium of claim 1 , wherein the instructions to add the charge storage elements and switching elements to the power frame direct the processing system to:

insert a charge storage element and corresponding switching elements between each power rail belonging to an isolated section and the power frame.

3. The medium of claim 1 , wherein the instructions to add the charge storage elements and switching elements to the power frame direct the processing system to:

insert a charge storage element and corresponding switching elements between each ground rail belonging to an isolated section and the power frame.

4. The medium of claim 1 , wherein the instructions to identify the attach ratio and place the standard cells in groupings further direct the processing system to:

determine an optimized attachment arrangement based on mitigating dependence of switching to one or both of power consumption and electromagnetic radiation.

5. The medium of claim 1 , wherein the instructions to identify the attach ratio and place the standard cells in groupings further direct the processing system to:

optimize placement based on number of gates in a grouping.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 20, 2019
From: YANAMADALA, SUBBAYYA CHOWDARY; YANNETTE, DANIEL F.; MYERS, BRENT ARNOLD
To: CHAOLOGIX, INC.
Reel/Frame 050103/0449 →
Continuity (2)
Provisional Application 62292685 · Feb 8, 2016
Related Publication 20190042688A1 · Feb 7, 2019