Coil pattern, method for forming same, and chip device including same
Provided is a method of forming a coil pattern on at least one surface on a substrate, the method comprising forming a seed layer on at least one surface of a substrate, and forming at least two or more plating layers to cover the seed layer, wherein the two or more plating layers are formed through anisotropic plating.
1. A method of forming a coil pattern on at least one surface on a substrate, the method comprising:
forming a seed layer on at least one surface of a substrate; and
forming at least two or more plating layers to cover the seed layer, wherein
the two or more plating layers are formed through anisotropic plating.
2. The method of claim 1 , wherein the seed layer is formed in a spiral shape.
3. The method of claim 2 , wherein said at least two or more plating layers are formed after at least two or more photosensitive film patterns are respectively formed on the substrate so as to be spaced apart from innermost and outer most sides of the seed layer.
4. The method of claim 3 , wherein a ratio of a height of said at least two or more photosensitive film patterns to a total width of said at least two or more plating layers is approximately 1:0.5 to 1:2.
5. The method of claim 3 , wherein the coil pattern is formed in an aspect ratio of approximately 2 to approximately 10.
6. The method of claim 5 , wherein the coil pattern has at least one region formed in a different width.
7. The method of claim 6 , wherein the coil pattern is formed to have a width gradually increasing or decreasing from an innermost side toward an outermost side.
8. The method of claim 7 , wherein the coil pattern has at least one region formed to have widths different from each other in lower end portion, middle portion, and upper end portion of the region.
9. A coil pattern formed by the method set forth in claim 1 , and comprising:
a seed layer formed on at least one surface of a substrate; and
at least two or more plating layers formed to cover the seed layer and formed through an anisotropic plating process performed at least twice.
10. The coil pattern of claim 9 , wherein the coil pattern is formed to have a width gradually increased or decreased from an innermost side thereof toward an outermost side thereof.
11. The coil pattern of claim 10 , wherein the coil pattern has at least one region formed to have widths different from each other in lower end portion, middle portion, and upper end portion of the region.
12. The coil pattern of claim 11 , wherein when a width of an innermost portion of the coil pattern is A, a width of a central portion of the coil pattern is B, a width of an outermost portion of the coil pattern is C, the upper end portion is formed to have a relationship B≥C>A, the middle portion is formed to have a relationship C>B≥A, and the lower end portion is formed in a relationship C>B≥A.
13. A chip device comprising:
a body;
at least one substrate provided in the body;
at least one coil pattern formed on at least one surface of the substrate; and
an insulating layer formed between the coil pattern and the body, wherein
the coil pattern comprises a seed layer formed on at least one surface of the substrate and at least two or more plating layers formed to cover the seed layer and formed through an anisotropic process performed at least twice.
14. The chip device of claim 13 , wherein at least some regions of the substrate are removed and the removed regions are filled with the body.
15. The chip device of claim 13 , wherein the coil pattern is formed to have a width gradually increased or decreased from an innermost side thereof toward an outermost side thereof.
16. The chip device of claim 13 , wherein when a width of an innermost portion of the coil pattern is A, a width of a central portion of the coil pattern is B, a width of an outermost portion of the coil pattern is C, the upper end portion is formed to have a relationship B C>A, the middle portion is formed to have a relationship C>B≥A, and the lower end portion is formed in a relationship C>B≥A.
17. The chip device of claim 13 , wherein at least two substrates are provided to be laminated in a thickness direction of the body, and coil patterns respectively formed on the two or more substrates are connected in series or in parallel.
18. The chip device of claim 14 , wherein the coil pattern is formed to have a width gradually increased or decreased from an innermost side thereof toward an outermost side thereof.
19. The chip device of claim 14 , wherein when a width of an innermost portion of the coil pattern is A, a width of a central portion of the coil pattern is B, a width of an outermost portion of the coil pattern is C, the upper end portion is formed to have a relationship B≥C>A, the middle portion is formed to have a relationship C>B≥A, and the lower end portion is formed in a relationship C>B≥A.
20. The chip device of claim 14 , wherein at least two substrates are provided to be laminated in a thickness direction of the body, and coil patterns respectively formed on the two or more substrates are connected in series or in parallel.