IP Library › Granted Patent US 11,158,511
Granted Patent B2
US 11,158,511 · App. 16/078,938 · Granted Oct 26, 2021

Semiconductor device and power converter including a copper film with a small grain size stress relaxtion layer

Inventors: Kazuyuki Sugahara (Tokyo, JP); Hiroaki Okabe (Tokyo, JP); Motoru Yoshida (Tokyo, JP)
Assignee: MITSUBISHI ELECTRIC CORPORATION
H01L21/28H01L21/3205H01L21/76H01L21/768H01L23/522H01L29/12H01L29/739H01L29/78
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,158,511
App. No.
16/078,938
Granted
Oct 26, 2021
Kind
B2
Abstract

A semiconductor device that includes a semiconductor layer disposed on a semiconductor substrate, a first semiconductor region provided in an upper layer portion of the semiconductor layer, a second semiconductor region provided in an upper layer portion of the first semiconductor region, a gate insulation film, a gate electrode, a first main electrode that is provided on an interlayer insulation film that covers the gate electrode and that is electrically connected to the second semiconductor region via a contact hole, and a second main electrode disposed on a second main surface of the semiconductor substrate. The first main electrode includes an underlying electrode film connected to the second semiconductor region via the contact hole, and a copper film provided on the underlying electrode film. The copper film includes at least a portion that serves as a stress relaxation layer having a smaller grain size than the other portion of the copper film.

Claims (31)

1. A semiconductor device comprising:

a semiconductor substrate;

a semiconductor layer of a first conductivity type disposed on a first main surface of the semiconductor substrate;

a first semiconductor region of a second conductivity type selectively provided in an upper layer portion of the semiconductor layer;

a second semiconductor region of the first conductivity type selectively provided in an upper layer portion of the first semiconductor region;

a gate insulation film provided in contact with surfaces of the first and second semiconductor regions and the semiconductor layer;

an insulation film that is thicker than the gate insulation film and provided in a region of the semiconductor layer in which the gate insulation film is not provided;

a gate electrode provided on at least the gate insulation film;

an interlayer insulation film provided to cover the gate electrode;

a contact hole formed through the gate insulation film and the interlayer insulation film and exposing at least the second semiconductor region at a bottom thereof;

a first main electrode provided on the interlayer insulation film and electrically connected to the second semiconductor region via the contact hole; and

a second main electrode disposed on a second main surface of the semiconductor substrate,

wherein the first main electrode includes:

an underlying electrode film connected to the second semiconductor region via the contact hole; and

a copper film provided on the underlying electrode film, and

the copper film has a thickness greater than or equal to 15 μm, and

the copper film includes a stress relaxation layer which is outside of said contact hole and has a smaller grain size than another portion of the copper film, the stress relaxation layer being above a region that includes at least a junction between the gate insulation film and the insulation film.

2. The semiconductor device according to claim 1 , further comprising:

an external connection line electrically connected to the copper film; and

the sealing resin provided on the copper film that includes the external connection line,

wherein the stress relaxation layer is provided at a junction between the sealing resin and the copper film.

3. The semiconductor device according to claim 1 , wherein

the grain size of the stress relaxation layer is in a range of 0.1 to 1 μm.

4. The semiconductor device according to claim 1 , wherein

the underlying electrode film includes asperities on at least a part of a surface in contact with the copper film.

5. The semiconductor device according to claim 1 , wherein

the semiconductor substrate is a silicon carbide semiconductor substrate.

6. A power converter comprising:

a main converter circuit that includes the semiconductor device according to claim 1 and converts and outputs input power;

a drive circuit that outputs a driving signal for driving the semiconductor device to the semiconductor device; and

a control circuit that outputs a control signal for controlling the drive circuit to the drive circuit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 22, 2018
From: SUGAHARA, KAZUYUKI; OKABE, HIROAKI; YOSHIDA, MOTORU
To: MITSUBISHI ELECTRIC CORPORATION
Reel/Frame 046910/0620 →
Priority Claims (1)
JP JP2016-067388 · Mar 30, 2016 · national
Continuity (1)
Related Publication 20190057873A1 · Feb 21, 2019