High density multiple die structure
Apparatus and methods are provided for integrated circuit packages having a low z-height. In an example, a method can include mounting a first integrated circuit sub-package to a first package substrate wherein the sub-package substrate spans an opening of the first package substrate, mounting a second integrated circuit package to a second package substrate, and mounting the first package substrate with the second package substrate wherein the mounting includes locating a portion of the second integrated circuit package within the opening of the first package substrate.
1. An integrated circuit package system comprising:
a first substrate having an opening;
a first integrated circuit package including one or more first dies forming a direct interface with the first substrate and configured to span the opening and define a volume;
a second substrate;
a second integrated circuit memory package mounted to the second substrate;
wherein the first substrate is mounted to the second substrate, wherein the second substrate is dimensioned larger than the opening;
wherein the second integrated circuit memory package is configured to occupy at least a portion of the volume;
wherein the first integrated circuit package includes a first plurality of wire bonds electrically coupling the one or more first dies with the first substrate; and
an adhesive configured to secure the first integrated circuit package with the first substrate, wherein at least a portion of the adhesive is located at an interface of the opening and an underside of the first integrated circuit package.
2. The integrated circuit package system of claim 1 , wherein the first integrated circuit package includes a stack of non-volatile memory dies.
3. The integrated circuit package system of claim 1 , wherein the second integrated circuit package includes a second stack of integrated circuit dies.
4. The integrated circuit package system of claim 3 , wherein the second stack of integrated circuit dies includes a volatile memory die.
5. The integrated circuit package system of claim 3 , wherein the second stack of integrated circuit dies includes an application specific integrated circuit (ASIC).
6. The integrated circuit package system of claim 1 , including a first overmold configured to encapsulate the first integrated circuit package and a top surface of the first substrate.
7. The integrated circuit package system of claim 6 , wherein the first overmold is configured to encapsulate first wire bonds electrically connecting the first integrated circuit package with the first substrate.
8. The integrated circuit package system of claim 6 , including a second overmold configured to encapsulate the second integrated circuit package and at least a portion of a top surface of the second substrate.
9. The integrated circuit package system of claim 8 , wherein the second overmold is configured to encapsulate second wire bonds electrically connecting the second integrated circuit package with the second substrate.
10. An electronic package comprising:
a first substrate;
a first integrated circuit package mounted on the first substrate;
a second substrate mounted on a periphery of the first substrate, the second substrate including an opening configured to surround the first integrated circuit package when the second substrate is mounted to the first substrate;
a second integrated circuit package including one or more dies forming a direct interface with the second substrate, the second integrated circuit package configured to span the opening;
wherein the second integrated circuit package includes a plurality of wire bonds electrically coupling the one or more dies to the second substrate; and
an adhesive configured to secure the first integrated circuit package with the first substrate, wherein at least a portion of the adhesive is located at an interface of the opening and an underside of the first integrated circuit package.
11. The electronic package of claim 10 , wherein the first integrated circuit package includes a first stack of integrated circuit dies.
12. The electronic package system of claim 11 , wherein the first stack of integrated circuit dies includes a volatile memory die.
13. The electronic package system of claim 12 , wherein the first stack of integrated circuit dies includes an application specific integrated circuit (ASIC).
14. The electronic package system of claim 10 , wherein the second integrated circuit package includes a stack of non-volatile memory dies.