Semiconductor storage device

1. A semiconductor storage device, comprising:

a memory unit that includes a plurality of memory cells;

an address latch unit that receives an address and an active command that is applied to the memory cells designated by the address, and latches the address at the time of receiving the active command whenever the active command is received;

a refresh control unit that instructs a memory access control unit to execute a regular refresh operation based on a refresh command with respect to the memory unit in the case of receiving the refresh command, and instructs the memory access control unit to execute an interrupt refresh operation, which is a refresh operation based on the address latched by the address latch unit, with respect to a nearby address of the address; and

the memory access control unit that executes the regular refresh operation and the interrupt refresh operation continuously with respect to the memory unit responding to one time of executing the refresh command on the basis of the instruction from the refresh control unit.

2. The semiconductor storage device according to claim 1 , further comprising:

a monitor unit that monitors the active command that is received, and prevents the refresh control unit from instructing the memory access control unit to perform the interrupt refresh operation in a case where the active command is not received after receiving the refresh command.

3. The semiconductor storage device according to claim 1 ,

wherein the nearby address of the address at the time of receiving the active command is either an address obtained by incrementing the address at the time of receiving the active command by “+1” or an address obtained by decrementing the address at the time of receiving the active command by “−1”.

4. The semiconductor storage device according to claim 1 ,

wherein the active command is a command that activates a word line of the memory unit, and includes at least a read command, a write command, and a refresh command.

5. A semiconductor storage device, comprising:

a memory unit that includes a plurality of memory cells;

an address latch unit that receives an address and an active command that is applied to the memory cells designated by the address, latches the address at the time of receiving the active command whenever the active command is received, and retains n latched addresses;

a refresh control unit that instructs a memory access control unit to execute a regular refresh operation based on a refresh command on the memory unit in the case of receiving the refresh command, and instructs the memory access control unit to execute an interrupt refresh operation, which is a refresh operation based on one or more addresses latched by the address latch unit, on a nearby address of one of the one or more addresses; and

the memory access control unit that executes the regular refresh operation and the interrupt refresh operation on the memory unit on the basis of the instruction from the refresh control unit,

wherein the address latch unit is reset in a case where the memory access control unit executes the interrupt refresh operation, and enters a state capable of latching a subsequent address at the time of receiving a subsequent active command, and

wherein n is a natural number of two or three or more.

6. The semiconductor storage device according to claim 5 ,

wherein in the address latch unit, in a case where the memory access control unit executes the interrupt refresh operation, only an address that becomes the basis of the interrupt refresh operation is reset, and the address latch unit enters a state capable of latching an address at the time of receiving the subsequent active command.

7. The semiconductor storage device according to claim 5 ,

wherein the refresh control unit instructs the memory access control unit to execute an interrupt refresh operation, which is a refresh operation based on any one address of the addresses latched by the address latch unit, with respect to only a nearby address of the one address, and

in the address latch unit, in a case where the refresh control unit executes the interrupt refresh operation, the only one address that becomes the basis of the interrupt refresh operation is reset, and the address latch unit enters a state capable of latching an address at the time of receiving the subsequent active command.

8. The semiconductor storage device according to claim 5 , further comprising:

a monitor start unit that allows a latch operation of the address latch unit to be initiated after receiving m pieces of the active command from reception of the refresh command,

wherein m is a natural number.

9. The semiconductor storage device according to claim 8 ,

wherein the monitor start unit

allows a latch operation of the address latch unit to be initiated after receiving arbitrary k pieces of the active commands from reception of the refresh command, and

wherein k is an arbitrary natural number.

10. The semiconductor storage device according to claim 5 , further comprising:

an access count address latch unit that receives an address and an active command that is applied to the memory cells designated by the address, monitors the address at the time of receiving the active command, and counts the number of times of access with respect to the same address; and

an upper limit determination unit that allows the address latch unit to latch the same address in a case where the number of times of access to the same address, which is counted by the access count address latch unit, exceeds a predetermined value.

11. The semiconductor storage device according to claim 1 , further comprising:

an address comparison unit that compares the address at the time of receiving the active command and an address that is latched already by the address latch unit, and allows the address latch unit to execute a latch operation in a case where the addresses are different from each other from a result of the comparison.

12. The semiconductor storage device according to claim 11 ,

wherein in a case where a refresh address when the refresh control unit instructs the memory access control unit to perform the regular refresh operation is a nearby address of the address that is latched by the address latch unit, the address comparison unit resets the address that is latched by the address latch unit.

13. The semiconductor storage device according to claim 5 , further comprising:

an address comparison unit that compares less than n pieces of addresses which are latched already by the address latch unit and the address at the time of receiving the active command, and allows the address latch unit to execute a latch operation of an address at the time of newly receiving the active command only in a case where the addresses are different from each other from a result of the comparison.