IP Library › Granted Patent US 10,586,919
Granted Patent B2
US 10,586,919 · App. 16/094,265 · Granted Mar 10, 2020

Memory device

Inventors: Jea Gun Park (Seongnam-si, KR); Du Yeong Lee (Seoul, KR); Seung Eun Lee (Seoul, KR); Min Su Jeon (Seongnam-si, KR); Jong Ung Baek (Seongnam-si, KR); Tae Hun Shim (Suwon-si, KR)
Assignee: Industry-University Cooperation Foundation Hanyang University
H01L43/10G11C11/161H01L43/02H01L43/08H01L43/12
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Quick Facts
Patent No.
US 10,586,919
App. No.
16/094,265
Granted
Mar 10, 2020
Kind
B2
Abstract

A memory device in which lower electrodes, a buffer layer, a seed layer, a magnetic tunnel junction, a capping layer, synthetic antiferromagnetic layers, and an upper electrode are formed on a substrate in a laminated manner. The lower electrodes and the seed layer are formed of a polycrystalline conductive material, and the perpendicular magnetic anisotropy of the magnetic tunnel junction is maintained upon heat treatment at a high temperature of 400° C. or more.

Claims (22)

1. A memory device in which lower electrodes, a buffer layer, a seed layer, a magnetic tunnel junction, a capping layer, synthetic antiferromagnetic layers, and an upper electrode are formed on a substrate in a laminated manner, wherein the lower electrodes and the seed layer are formed of a polycrystalline conductive material,

wherein the seed layer is formed of a material which crystallizes at a temperature of 400° C. or higher.

2. The memory device according to claim 1 , wherein the lower electrodes are formed by laminating first and second lower electrodes.

3. The memory device according to claim 2 , wherein the first lower electrode is formed of a material comprising tungsten, and the second lower electrode is formed of a material comprising TiN.

4. The memory device according to claim 1 , wherein the seed layer is formed of a material comprising tungsten.

5. The memory device according to claim 4 , wherein the seed layer is formed to have a thickness of 1 nm to 3 nm.

6. The memory device according to claim 5 , wherein the buffer layer is formed of a material comprising tantalum.

7. The memory device according to claim 6 , wherein the buffer layer is formed to have a thickness of 2 nm to 10 nm.

8. The memory device according to claim 7 , wherein the capping layer is formed of a material comprising tantalum or tungsten.

9. The memory device according to claim 8 , wherein the capping layer comprising tungsten is formed to have a thickness of 0.35 nm to 0.55 nm.

10. A memory device in which lower electrodes, a buffer layer, a seed layer, a magnetic tunnel junction, a capping layer, synthetic antiferromagnetic layers, and an upper electrode are formed on a substrate in a laminated manner, wherein the lower electrodes and the seed layer are formed of a polycrystalline conductive material; and

wherein the magnetic tunnel junction has a squareness of magnetization change of more than 0.8 and 1 or less after heat treatment at 400° C. or higher.

11. A memory device in which lower electrodes, a buffer layer, a seed layer, a magnetic tunnel junction, a capping layer, synthetic antiferromagnetic layers, and an upper electrode are formed on a substrate in a laminated manner, wherein the lower electrodes comprise a laminated structure of tungsten and TiN, the buffer layer comprises tantalum, and the seed layer comprises tungsten.

12. The memory device according to claim 11 , wherein the seed layer is formed to have a thickness of 1 nm to 3 nm.

13. The memory device according to claim 11 , wherein the buffer layer is formed to have a thickness of 2 nm to 10 nm.

14. The memory device according to claim 11 , wherein the capping layer is formed of a material comprising tantalum or tungsten.

15. The memory device according to claim 14 , wherein the capping layer comprising tungsten is formed to have a thickness of 0.35 nm to 0.55 nm.

16. The memory device according to claim 11 , wherein the magnetic tunnel junction has a squareness of magnetization change of more than 0.8 and 1 or less after heat treatment at 400° C. or higher.

17. A method of fabricating a memory device, comprising:

a step of forming lower electrodes, a buffer layer, a seed layer, a magnetic tunnel junction, a capping layer, synthetic antiferromagnetic layers, and an upper electrode on a substrate in a laminated manner; and

a step of performing heat treatment at 400° C. to 500° C.,

wherein the lower electrodes comprise a laminated structure of tungsten and TiN; the buffer layer and the seed layer comprise tantalum and tungsten; and the heat treatment is performed after the upper electrode is formed.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 17, 2018
From: PARK, JEA GUN; LEE, DU YEONG; LEE, SEUNG EUN; JEON, MIN SU; BAEK, JONG UNG; SHIM, TAE HUN
To: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY
Reel/Frame 047198/0723 →
Priority Claims (2)
KR 10-2014-0046563 · Apr 18, 2014 · national
KR 10-2014-0102139 · Aug 8, 2014 · national
Continuity (1)
Related Publication 20190229259A1 · Jul 25, 2019