Circuit structure for suppressing surge current

1. A circuit structure for suppressing surge current, the circuit structure comprising:

a surge current suppression judgment circuit;

a switching control circuit; and

a self-boosting regulating circuit, wherein

an output end of the surge current suppression judgment circuit is connected with the switching control circuit, an output end of the switching control circuit is connected with the self-boosting regulating circuit, the switching control circuit and the self-boosting regulating circuit are both connected with a current input end Vin, an output end of the self-boosting regulating circuit is connected with an input end of the surge current suppression judgment circuit, the output end of the self-boosting regulating circuit is an output end Vout of the whole circuit structure for suppressing surge current,

wherein the surge current suppression judgment circuit comprises an operational amplifier M 1 , a resistor R 1 and a resistor R 2 , wherein

one end of the resistor R 1 and one end of the resistor R 2 are both connected with a non-inverting input end of the operational amplifier M 1 , the other end of the resistor R 1 is connected with a power supply of 12V, the other end of the resistor R 2 is grounded, an inverting input end of the operational amplifier M 1 is connected with the output end of the self-boosting regulating circuit, a positive power supply end of the operational amplifier M 1 is connected with the power supply of 12V, a negative power supply end of the operational amplifier M 1 is grounded; an output pin of the operational amplifier M 1 is connected with the switching control circuit.

2. The circuit structure for suppressing surge current according to claim 1 , wherein the switching control circuit comprises a resistor R 3 , a resistor R 4 , an N type field effect transistor Q 1 , an N type field effect transistor Q 2 and a P type field effect transistor Q 3 , wherein

a D pin of the N type field effect transistor Q 1 is connected with the current input end Vin, a B pin and a S pin of the N type field effect transistor Q 1 are both connected with the output end Vout, a G pin of the N type field effect transistor Q 1 is connected with a S pin of the N type field effect transistor Q 2 and a D pin of the P type field effect transistor Q 3 ;

a D pin of the N type field effect transistor Q 2 is connected with one end of the resistor R 3 and one end of the resistor R 4 , the other end of the resistor R 3 is connected with a power supply of 12V, the other end of the resistor R 4 is grounded, a G pin of the N type field effect transistor Q 2 is connected with the output pin of the operational amplifier M 1 and a G pin of the P type field effect transistor Q 3 ; and

a B pin and a S pin of the P type field effect transistor Q 3 are both connected with the self-boosting regulating circuit.

3. The circuit structure for suppressing surge current according to claim 2 , wherein the self-boosting regulating circuit comprises a capacitor C 1 and a diode D 1 , wherein an anode of the diode is connected with the current input end Vin, a cathode of the diode is connected with the B pin and the S pin of the P type field effect transistor Q 3 and one end of the capacitor C 1 , and the other end of the capacitor Cl is connected with the output end Vout.