DRAM with buried gate structure
View Patent ↗A semiconductor structure for a memory device includes a substrate including a memory cell region and a peripheral circuit region defined thereon, at least an active region formed in the peripheral circuit region, a buried gate structure formed in the active region in the peripheral circuit region, a conductive line structure formed on the buried gate structure, and at least a bit line contact plug formed in the memory cell region.
1. A semiconductor structure for a memory device comprising:
a substrate comprising a memory cell region and a peripheral circuit region defined thereon;
multiple active regions formed in the peripheral circuit region;
a buried gate structure formed in the active regions;
a conductive line structure formed right above the buried gate structure, wherein the conductive line structure completely overlaps the buried gate structure, and a longitudinal axis of the conductive line structure and a longitudinal axis of the buried gate structure extend in a same horizontal direction parallel to a surface of the substrate across the active regions, and an insulating layer is sandwiched between the buried gate structure and the conductive line structure, and the buried gate structure and the conductive line structure are physically spaced apart and electrically isolated from each other by the insulating layer; and
at least a bit line formed in the memory cell region, wherein a top surface of bit line in the memory cell region is leveled with a top surface of the conductive line structure in the peripheral circuit region.
2. The semiconductor structure for the memory device according to claim 1 , further comprising a local inter connection structure electrically connecting the conductive line structure and each of the active regions in the peripheral circuit region.
3. The semiconductor structure for the memory device according to claim 2 , wherein the local inter connection structure comprises:
at least a first contact plug formed on the conductive line structure;
at least a second contact plug formed on each of the active regions at a first side of the buried gate structure; and
at least a connecting layer electrically connecting the first contact plug and the second contact plug.
4. The semiconductor structure for the memory device according to claim 3 , wherein the second contact plug comprises a contact plug upper portion and a contact plug lower portion.
5. The semiconductor structure for the memory device according to claim 4 , wherein a top surface of the contact plug lower portion of the second contact plug is leveled with a top surface of the conductive line structure.
6. The semiconductor structure for the memory device according to claim 4 , wherein the contact plug upper portion and the first contact plug comprise a same material, and the contact plug lower portion and the conductive line structure comprise a same material.
7. The semiconductor structure for the memory device according to claim 3 , further comprising an interconnection structure formed on each of the active regions at a second side of the buried gate structure opposite to the first side.
8. The semiconductor structure for the memory device according to claim 7 , wherein the interconnection structure electrically connecting each of the active regions to a bit line, or alternatively electrically connecting each of the active regions to a bit line bar (/BL).