IP Library › Granted Patent US 10,566,280
Granted Patent B2
US 10,566,280 · App. 16/103,106 · Granted Feb 18, 2020

Semiconductor device and method of manufacturing the same

Inventors: Satoshi Wakatsuki (Yokkaichi, JP); Masayuki Kitamura (Yokkaichi, JP); Takeshi Ishizaki (Nagoya, JP); Hiroshi Itokawa (Kuwana, JP); Daisuke Ikeno (Yokkaichi, JP); Kei Watanabe (Yokkaichi, JP); Atsuko Sakata (Yokkaichi, JP)
Assignee: TOSHIBA MEMORY CORPORATION
H01L23/5227H01L21/76846H01L21/76877H01L23/53266H01L27/1157H01L27/11582H01L29/40117
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Quick Facts
Patent No.
US 10,566,280
App. No.
16/103,106
Granted
Feb 18, 2020
Kind
B2
Abstract

In one embodiment, a semiconductor device includes a first insulator. The device further includes a metal layer that includes a first metal layer provided on a surface of the first insulator, and a second metal layer provided on a surface of the first metal layer and containing a first metallic element and oxygen or containing aluminum and nitrogen, or includes a third metal layer provided on the surface of the first insulator and containing a second metallic element, aluminum and nitrogen. The device further includes an interconnect material layer provided on a surface of the metal layer.

Claims (38)

1. A semiconductor device comprising:

a first insulator;

a metal layer that includes a first metal layer provided on a surface of the first insulator, and a second metal layer provided on a surface of the first metal layer and containing a first metallic element and oxygen or containing aluminum and nitrogen, or includes a third metal layer provided on the surface of the first insulator and containing a second metallic element, aluminum and nitrogen;

an interconnect material layer provided on a surface of the metal layer;

a charge storage layer provided on a surface of the metal layer via the first insulator, the charge storage layer being different from the metal layer; and

a semiconductor layer provided on a surface of the charge storage layer via a second insulator.

2. The device of claim 1 , wherein the second metal layer is an aluminum oxide film, a titanium oxide film, a tantalum oxide film, a hafnium oxide film, a zirconium oxide film or an aluminum nitride film.

3. The device of claim 1 , wherein the first metal layer contains titanium and nitrogen.

4. The device of claim 1 , wherein the first insulator contains aluminum and oxygen.

5. The device of claim 1 , wherein the second metallic element is titanium, tantalum, hafnium, zirconium, vanadium or niobium.

6. The device of claim 1 , wherein a ratio of concentration of aluminum to a total concentration of the second metallic element and aluminum in the third metal layer is 0.55 to 0.75.

7. The device of claim 1 , wherein the second metal layer further contains a semiconductor element.

8. The device of claim 1 , wherein the interconnect material layer further contains nitrogen.

9. The device of claim 8 , wherein a nitrogen concentration in the interconnect material layer is 1×10 19 to 2×10 20 atoms/cm 3 .

10. The device of claim 1 , wherein the interconnect material layer further contains fluorine and/or chlorine.

11. The device of claim 10 , wherein a fluorine concentration and/or a chlorine concentration in the interconnect material layer is 1×10 18 atoms/cm 3 or less.

12. The device of claim 10 , wherein the interconnect material layer includes a first interconnect material layer that contains chlorine, and a second interconnect material layer that contains fluorine.

13. The semiconductor device comprising:

a first insulator;

a metal layer provided on a surface of the first insulator and containing aluminum and oxygen or containing aluminum and nitrogen;

an interconnect material layer in contact with a surface of the metal layer and containing nitrogen;

a charge storage layer provided on a surface of the metal layer via the first insulator, the charge storage layer being different from the metal layer; and

a semiconductor layer provided on a surface of the charge storage layer via a second insulator.

14. The device of claim 13 , wherein the interconnect material layer further contains fluorine and/or chlorine.

15. The device of claim 14 , wherein the interconnect material layer includes a first interconnect material layer that contains nitrogen and chlorine, and a second interconnect material layer that contains nitrogen and fluorine.

16. A method of manufacturing a semiconductor device, comprising:

forming a first insulator;

successively forming a charge storage layer, a second insulator, and a semiconductor layer on a surface of the first insulator;

forming a metal layer that includes a first metal layer provided on a surface of the first insulator, and a second metal layer provided on a surface of the first metal layer and containing a first metallic element and oxygen or containing aluminum and nitrogen, or includes a third metal layer provided on the surface of the first insulator and containing a second metallic element, aluminum and nitrogen, the metal layer being different from the charge storage layer; and

forming an interconnect material layer on a surface of the metal layer.

17. The method of claim 16 , wherein the second metal layer is an aluminum oxide film, a titanium oxide film, a tantalum oxide film, a hafnium oxide film, a zirconium oxide film or an aluminum nitride film.

18. The method of claim 16 , wherein the interconnect material layer further contains nitrogen.

19. The method of claim 16 , wherein the interconnect material layer further contains fluorine and/or chlorine.

20. A semiconductor device comprising:

an interconnect;

a first insulator provided on a surface of the interconnect;

a metal layer that includes a first metal layer provided on a surfaces of the interconnect and the first insulator, and a second metal layer provided on a surface of the first metal layer and containing a first metallic element and oxygen or containing aluminum and nitrogen, or includes a third metal layer provided on the surfaces of the interconnect and the first insulator and containing a second metallic element, aluminum and nitrogen, the metal layer being different from the interconnect and electrically connected to the interconnect; and

an interconnect material layer provided on a surface of the metal layer.

Assignments (4)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 14, 2018
From: WAKATSUKI, SATOSHI; KITAMURA, MASAYUKI; ISHIZAKI, TAKESHI; ITOKAWA, HIROSHI; IKENO, DAISUKE; WATANABE, KEI; SAKATA, ATSUKO
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 046798/0070 →
Priority Claims (1)
JP 2018-043090 · Mar 9, 2018 · national
Continuity (1)
Related Publication 20190279932A1 · Sep 12, 2019