Semiconductor device
View Patent ↗A memory device is disclosed that includes memory cell, e strap cell, conductive segment, and logic cell. The strap cell is arranged abutting the memory cell. The strap cell includes an active region, a first gate, and a second gate. The first gate is arranged across the active region. The second gate is arranged across the active region and disposed at the end of active region. The conductive segment is disposed over the first gate and the second gate. The strap cell is disposed between the memory cell and the logic cell, and the logic cell includes a third gate. The conductive segment is spaced apart from the third gate, and the length of the conductive segment is smaller than five times of a gate pitch between the first gate and the second gate.
1. A semiconductor device, comprising:
at least one memory cell;
at least one strap cell abutting the at least one memory cell, the at least one strap cell comprising:
an active region;
a first gate arranged across the active region;
a second gate arranged across the active region and disposed at an end of the active region; and
at least one conductive segment disposed over the first gate and the second gate; and
at least one logic cell, wherein the at least one strap cell is disposed between the at least one memory cell and the at least one logic cell, and the at least one logic cell comprises a third gate;
wherein the at least one conductive segment of the at least one strap cell is spaced apart from the third gate of the at least one logic cell, and a length of the at least one conductive segment of the at least one strap cell is smaller than five times of a gate pitch between the first gate and the second gate of the at least one strap cell.
2. The semiconductor device of claim 1 , wherein the third gate is disposed next to the second gate without a gate therebetween.
3. The semiconductor device of claim 2 , wherein the length of the at least one conductive segment is approximately 1.5 times the gate pitch.
4. The semiconductor device of claim 1 , wherein the at least one strap cell further comprises:
a fourth gate disposed between the second gate and the third gate;
wherein the at least one conductive segment is disposed over the first gate, the second gate, and the fourth gate.
5. The semiconductor device of claim 1 , wherein the at least one strap cell further comprises:
a fourth gate disposed between the second gate and the third gate and disposed next to the second gate; and
a fifth gate disposed between the fourth gate and the third gate;
wherein the at least one conductive segment is disposed over the first gate, the second gate, the fourth gate, and the fifth gate.
6. The semiconductor device of claim 1 , wherein the length of the at least one conductive segment is in a range of approximately 0.085 micrometers and approximately 0.289 micrometers.
7. The semiconductor device of claim 1 , wherein the length of the at least one conductive segment is equal to a width of the at least one strap cell.
8. A semiconductor device, comprising:
a strap cell disposed between a memory cell and a logic cell, the strap cell comprising:
an active region;
a plurality of gates comprising a first gate, a second gate, and at most three dummy gates, wherein the first gate and the second gate are arranged across the active region, and the second gate is disposed at an end of the active region and is disposed next to the first gate, and the dummy gates are not arranged across the active region; and
at least one conductive segment disposed over the first gate, the second gate, and at most two of the dummy gates,
wherein the second gate and the at most three dummy gates of the strap cell are spaced apart from each other evenly.
9. The semiconductor device of claim 8 , wherein the plurality of gates comprise no dummy gate, and the at least one conductive segment is arranged across the first gate, the second gate, and no dummy gate.
10. The semiconductor device of claim 9 , wherein a length of the at least one conductive segment is approximately 0.085 micrometers.
11. The semiconductor device of claim 8 , wherein the plurality of gates comprise a first dummy gate that is disposed next to the second gate, and
the at least one conductive segment is arranged across the first gate, the second gate, and the first dummy gate.
12. The semiconductor device of claim 8 , wherein
the plurality of gates comprise a first dummy gate that is disposed next to the second gate, and a second dummy gate that is disposed next to the first dummy gate, and
the at least one conductive segment is arranged across the first gate, the second gate, the first dummy gate, and the second dummy gate.
13. The semiconductor device of claim 8 , wherein a length of the at least one conductive segment is in a range of approximately 0.085 micrometers and approximately 0.289 micrometers, and a gate pitch between the first gate and the second gate is approximately 0.0575 micrometers.
14. The semiconductor device of claim 8 , wherein a length of the at least one conductive segment is in a range between a first length and a second length,
wherein the at least one conductive segment has the first length when the at least one conductive segment is arranged across no dummy gate, and the at least one conductive segment has the second length when the at least one conductive segment is arranged across two of the dummy gates.
15. The semiconductor device of claim 8 , wherein a length of the at least one conductive segment is smaller than four times a gate pitch between the first gate and the second gate.
16. The semiconductor device of claim 8 , wherein a length of the at least one conductive segment is equal to a width of the strap cell.
17. A semiconductor device, comprising:
a logic cell comprising a gate; and
a strap cell disposed separated from the logic cell and abutting a memory cell, the strap cell comprising:
an active area;
a first gate arranged across the active area;
a second gate arranged across the active area and disposed at an end of the active area; and
a conductive segment disposed over the first gate and the second gate and disposed apart from the gate of the logic cell,
wherein the first gate and the second gate of the strap cell and the gate of the logic cell are arranged in parallel with each other and spaced apart from each other evenly.
18. The semiconductor device of claim 17 , wherein the strap cell further comprises:
a dummy gate disposed next to the second gate,
wherein the dummy gate is not arranged across the active area, and
the conductive segment is disposed over the dummy gate.
19. The semiconductor device of claim 17 , wherein the strap cell further comprises:
a first dummy gate and a second dummy gate disposed between the second gate and the gate of the logic cell,
wherein the conductive segment is disposed across the first dummy gate and the second dummy gate, and
a gate pitch between the second gate and the first dummy gate is equal to a gate pitch between the first dummy gate and the second dummy gate.
20. The semiconductor device of claim 17 , wherein the strap cell further comprises:
at most three dummy gates disposed between the second gate and the gate of the logic cell,
wherein the conductive segment is disposed over at most two of the dummy gates.