IP Library Granted Patent US 10,510,580
Granted Patent B2
US 10,510,580 · App. 16/103,988 · Granted Dec 17, 2019

Dummy fin structures and methods of forming same

Inventors: Chin-Hsiang Lin (Hsinchu, TW); Keng-Chu Lin (Ping-Tung, TW); Shwang-Ming Jeng (Hsinchu, TW); Teng-Chun Tsai (Hsinchu, TW); Tsu-Hsiu Perng (Zhubei, TW); Fu-Ting Yen (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H01L21/76229H01L21/823431H01L21/823821H01L21/823878H01L21/823892H01L27/0924H01L29/6681H01L29/66545H01L29/66795H01L29/785
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Quick Facts
Patent No.
US 10,510,580
App. No.
16/103,988
Granted
Dec 17, 2019
Kind
B2
Abstract

An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.

Claims (42)

1. A method comprising:

depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate;

depositing a dielectric material over the first dielectric film;

recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material, wherein recessing the first dielectric film comprises etching the first dielectric film at a faster rate than the dielectric material; and

forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.

2. The method of claim 1 wherein depositing the dielectric material comprises covering a top surface of the first dielectric film with the dielectric material, the method further comprising planarizing the dielectric material to expose the first dielectric film.

3. The method of claim 2 , wherein depositing the dielectric material comprises defining a void under the dielectric material between the semiconductor fin and a second semiconductor fin.

4. The method of claim 1 further comprising prior to depositing the dielectric material, depositing a second dielectric film over the first dielectric film, and wherein the dummy fin comprises an upper portion formed of the second dielectric film.

5. The method of claim 1 further comprising:

prior to recessing the first dielectric film, recessing the dielectric material below a topmost surface of the first dielectric film;

depositing a second dielectric material over the dielectric material and the first dielectric film; and

planarizing the second dielectric material to expose the first dielectric film.

6. The method of claim 1 further comprising patterning the semiconductor substrate using a mask layer to define the semiconductor fin, wherein the first dielectric film is deposited over and along sidewalls of the mask layer.

7. The method of claim 1 further comprising:

patterning the semiconductor substrate using a mask layer to define the semiconductor fin; and

prior to depositing the first dielectric film, removing the mask layer.

8. A device comprising:

a first semiconductor fin and a second semiconductor fin extending upwards from a semiconductor substrate;

an isolation region comprising a first dielectric film and disposed between the first semiconductor fin and the second semiconductor fin;

a dummy fin extending upwards from the isolation region, wherein the dummy fin comprises:

a first dielectric material extending from below a topmost surface of the first dielectric film to above the topmost surface of the first dielectric film; and

a second dielectric film disposed between the first dielectric film and the first dielectric material; and

a gate stack disposed over and extending along sidewalls of the first semiconductor fin, over and along sidewalls of the second semiconductor fin, and over and along sidewalls of the dummy fin.

9. The device of claim 8 , wherein the first dielectric film comprises silicon oxide, and wherein the first dielectric material comprises a carbon containing oxide, a metal containing oxide, or a combination thereof.

10. The device of claim 8 , wherein a carbon percentage by weight of the second dielectric film is greater than a carbon percentage by weight of the first dielectric material.

11. The device of claim 8 , wherein a metal percentage by weight of the second dielectric film is greater than a metal percentage by weight of the first dielectric material.

12. The device of claim 8 , wherein the dummy fin further comprises a third dielectric material covering a top surface of the first dielectric material.

13. The device of claim 8 , wherein top surfaces of the dummy fin and the first semiconductor fin are substantially level.

14. The device of claim 8 , wherein the dummy fin extends higher than the first semiconductor fin.

15. The device of claim 8 further comprising a semiconductor mesa connecting the first semiconductor fin and the second semiconductor fin, wherein the isolation region further comprises a third dielectric material disposed between the first dielectric film and the semiconductor mesa, and wherein the third dielectric material further extends along sidewalls of the semiconductor mesa.

16. The device of claim 8 further comprising:

a second dummy fin disposed on an opposing side of the first semiconductor fin as the dummy fin, wherein the second dummy fin extends upwards from the isolation region, wherein the second dummy fin comprises the first dielectric material; and

a source/drain region disposed between the dummy fin and the second dummy fin.

17. A method comprising:

depositing a first dielectric film over and along sidewalls of a plurality of semiconductor fins;

depositing a dielectric material over the first dielectric film, wherein the dielectric material comprises carbon, metal, or a combination thereof, and wherein the dielectric material is deposited between each of the plurality of semiconductor fins;

planarizing the dielectric material to expose the first dielectric film;

etching the first dielectric film using an etchant that etches the first dielectric film at a faster rate than the dielectric material, wherein etching the first dielectric film defines a plurality of dummy fins extending above a top surface of the first dielectric film, and wherein the plurality of dummy fins comprises at least a portion of the dielectric material; and

forming a gate stack over and along sidewalls of the plurality of semiconductor fins and over and along sidewalls of the plurality of dummy fins.

18. The method of claim 17 further comprising prior to depositing the dielectric material, depositing a second dielectric film over the first dielectric film, wherein the second dielectric film comprises carbon, metal or a combination thereof, and wherein the plurality of dummy fins comprises at least a portion of the second dielectric film.

19. The method of claim 18 further comprising planarizing the second dielectric film to expose the first dielectric film.

20. The method of claim 17 further comprising forming a dielectric cap on a top surface of the first dielectric film, wherein the plurality of dummy fins comprises the dielectric cap.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 7, 2019
From: LIN, CHIN-HSIANG; LIN, KENG-CHU; TSAI, TENG-CHUN; PERNG, TSU-HSIU; YEN, FU-TING; JENG, SHWANG-MING
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 048269/0458 →
Continuity (2)
Provisional Application 62566045 · Sep 29, 2017
Related Publication 20190103304A1 · Apr 4, 2019
Cited By (3)
US 12,490,449 US 12,660,296 US 12,720,836