System, method and apparatus for executing instructions
A system, apparatus and method for ordering a sequence of processing transactions. The method includes accessing, from a memory, a program sequence of operations that are to be executed. Instructions are received, some of them having an identifier, or mnemonic, that is used to distinguish those identified operations from other operations that do not have an identifier, or mnemonic. The mnemonic indicates a distribution of the execution of the program sequence of operations. The program sequence of operations is grouped based on the mnemonic such that certain operations are separated from other operations.
1. A method comprising:
accessing a sequence of memory operations to be executed;
receiving a barrier instruction including a mnemonic that indicates a change in the sequence of memory operations;
evaluating the barrier instruction to identify the mnemonic;
executing the barrier instruction; and
modifying the sequence of memory operations based on the mnemonic, including:
separating the memory operations into a first group of non-coalesced memory operations and a second group of coalesced memory operations,
executing the first group of non-coalesced memory operations, and
executing the second group of coalesced memory operations after the first group of non-coalesced memory operations have been executed.
2. The method as claimed in claim 1 , further comprising:
assigning selected operations a metadata tag, based on the mnemonic.
3. The method as claimed in claim 2 , where the metadata tag determines the sequence of operations.
4. The method as claimed in claim 2 , where the metadata tag indicates a distinction in the distribution of operations.
5. The method as claimed in claim 2 , where the metadata tag includes an ordering tag.
6. The method as claimed in claim 1 , further comprising:
re-naming the mnemonic so subsequent operations have different metadata tag; and
coalescing operations based on the metadata tag.
7. The method as claimed in claim 1 , where the mnemonic includes an integer.
8. The method as claimed in claim 1 , where the receiving one or more instructions comprises receiving instructions via an interface.
9. The method as claimed in claim 1 , further comprising:
receiving a subsequent instruction including a mnemonic; and
modifying the mnemonic of the subsequent instruction.
10. The method as claimed in claim 1 , further comprising:
executing one or more operations having a mnemonic after a previous instruction is executed; and
coalescing one or more operations subsequent to executing an instruction having a mnemonic.
11. The method as claimed in claim 1 , where selected operations are executed independent of the mnemonic.
12. The method as claimed in claim 1 , further comprising:
coalescing memory operations based on a matching mnemonic.
13. The method as claimed in claim 1 , further comprising:
coalescing operations based on identified instructions independent of a mnemonic.
14. The method as claimed in claim 1 , where the mnemonic is a name, an identifier or a code.
15. The method as claimed in claim 14 , where the barrier instruction is not a memory operation, and the mnemonic is a name, and the barrier instruction increments a monotonically increasing counter that is used to assign an order tag to each memory operation in the sequence of memory operations.
16. The method as claimed in claim 15 , where the mnemonic name is separation (SEP).
17. An apparatus, comprising:
a memory; and
a processor, coupled to the memory, configured to:
access a sequence of memory operations to be executed;
receive a barrier instruction, having a mnemonic that indicates a change in the sequence of memory operations;
evaluate the barrier instruction to identify the mnemonic;
execute the barrier instruction; and
modify the sequence of memory operations based on the mnemonic, including:
separate the memory operations into a first group of non-coalesced memory operations and a second group of coalesced memory operations,
execute the first group of non-coalesced memory operations, and
execute the second group of coalesced memory operations after the first group of non-coalesced memory operations have been executed.