Semiconductor package
A semiconductor package includes a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface, an encapsulant encapsulating at least a portion of the semiconductor chip, and a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer and a via electrically connected to the connection pads of the semiconductor chip, wherein at least a portion of the redistribution layer and the via is formed of a metal layer having a concave portion depressed from a lower surface thereof and filled with an insulating material.
1. A semiconductor package comprising:
a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
an encapsulant encapsulating at least a portion of the semiconductor chip; and
a connection member disposed on the active surface of the semiconductor chip and including an insulating layer, a redistribution layer and a via, the redistribution layer and the via being electrically connected to the connection pads of the semiconductor chip,
wherein at least a portion of the redistribution layer and the via is formed of a metal layer having a concave portion depressed from a lower surface thereof, the concave portion being filled with an insulating material,
the metal layer includes a plating metal layer and a bonding metal layer disposed on a surface of the plating metal layer and exposed through the concave portion, and
the bonding metal layer is in contact with the insulating layer stacked on the lower surface of the metal layer on which the concave portion is formed.
2. The semiconductor package of claim 1 , wherein
the bonding metal layer disposed along an interface with the insulating layer.
3. The semiconductor package of claim 1 , wherein
the metal layer includes an inner bonding metal layer, a seed metal layer, the plating metal layer, and the bonding metal layer which are sequentially stacked.
4. The semiconductor package of claim 3 , wherein
the inner bonding metal layer and the bonding metal layer include titanium (Ti).
5. The semiconductor package of claim 3 , wherein
the seed metal layer and the plating metal layer include copper (Cu).
6. The semiconductor package of claim 3 , wherein
the inner bonding metal layer is in contact with the insulating layer.
7. The semiconductor package of claim 1 , wherein the insulating material fills the concave portion and horizontally extends on the redistribution layer and the via.
8. The semiconductor package of claim 1 , further comprising:
a core member having a through-hole,
wherein the semiconductor chip is disposed in the through-hole of the core member.
9. The semiconductor package of claim 8 , wherein
the core member includes a first core insulating layer, a first wiring layer in contact with the connection member and embedded in one side of the first core insulating layer, and a second wiring layer disposed on another side opposite to the one side of the first core insulating layer where the first wiring layer is embedded, and
the first and second wiring layers are electrically connected to the connection pads.
10. The semiconductor package of claim 9 , wherein the core member further includes:
a second core insulating layer disposed on the first core insulating layer and covering the second wiring layer and a third wiring layer disposed on the second core insulating layer at an opposite side of the second wiring layer.
11. The semiconductor package of claim 8 , wherein
the core member includes: a first core insulating layer and a first wiring layer and a second wiring layer disposed on both surfaces of the first core insulating layer, and
the first and second wiring layers are electrically connected to the connection pads.
12. The semiconductor package of claim 11 , wherein
the core member further includes a second core insulating layer, disposed on a lower surface of the first core insulating layer and covering the first wiring layer, and a third wiring layer disposed on the second core insulating layer at an opposite side of the first wiring layer, and
the third wiring layer is electrically connected to the connection pads.
13. The semiconductor package of claim 12 , wherein
the core member further includes a third core insulating layer, disposed on an upper surface of the first core insulating layer and covering the second wiring layer, and a fourth wiring layer disposed on the third core insulating layer at an opposite side of the second wiring layer, and
the fourth wiring layer is electrically connected to the connection pads.
14. A semiconductor package comprising:
a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
an encapsulant encapsulating at least a portion of the semiconductor chip; and
a connection member disposed on the active surface of the semiconductor chip and including a redistribution layer, a via electrically connected to the connection pads of the semiconductor chip, and an insulating layer,
wherein at least a portion of the redistribution layer or the via has a concave portion depressed from a lower surface thereof in contact with an insulting layer and is formed of a metal layer having a first bonding metal layer, a seed metal layer, a plating metal layer, and a second bonding metal layer which are sequentially stacked, and
the second bonding metal layer is exposed through the concave portion and in contact with the insulating layer.
15. The semiconductor package of claim 14 , wherein
the first and second bonding metal layers include titanium (Ti).