Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer
An SOI wafer contains a compressively stressed buried insulator structure. In one example, the stressed buried insulator (BOX) may be formed on a host wafer by forming silicon oxide, silicon nitride and silicon oxide layers so that the silicon nitride layer is compressively stressed. Wafer bonding provides the surface silicon layer over the stressed insulator layer. Preferred implementations of the invention form MOS transistors by etching isolation trenches into a preferred SOI substrate having a stressed BOX structure to define transistor active areas on the surface of the SOI substrate. Most preferably the trenches are formed deep enough to penetrate through the stressed BOX structure and some distance into the underlying silicon portion of the substrate. The overlying silicon active regions will have tensile stress induced due to elastic edge relaxation.
1. A CMOS device comprising n-channel MOSFETs (n-MOSFETs) and p-channel MOSFETs (p-MOSFETs), the n-MOSFETs and p-MOSFETs being formed in respective first regions and second regions of a surface semiconductor layer overlying a stressed buried structure; the n-MOSFETs having shallow trench isolation structures formed at ends of their respective source and drain regions, the shallow trench isolation structures being sufficiently deep to penetrate through an entire depth of the stressed buried structure thereby permitting elastic edge relaxation of the stressed buried structure underlying the first regions occupied by the n-MOSFETs, inducing longitudinal tensile strain in channels of the n-MOSFETs, and the p-MOSFETs not having shallow trench isolation structures formed at ends of their respective source and drain regions.
2. The CMOS device of claim 1 , wherein the stressed buried structure comprises a layer of compressively stressed silicon germanium underlying a layer of silicon oxide.
3. The CMOS device of claim 1 , wherein the surface semiconductor layer comprises a silicon layer.
4. The CMOS device of claim 1 , wherein the surface semiconductor layer comprises a germanium layer.
5. The CMOS device of claim 2 , wherein the surface semiconductor layer comprises a silicon layer.
6. The CMOS device of claim 2 , wherein the surface semiconductor layer comprises a germanium layer.
7. The CMOS device of claim 1 , wherein the surface semiconductor layer comprises a silicon germanium alloy layer.
8. The CMOS device of claim 2 , wherein the surface semiconductor layer comprises a silicon germanium alloy layer.
9. The CMOS device of claim 2 , further comprising silicon germanium stressors in respective source and drain regions of the p-MOSFETs, said silicon germanium stressors introducing longitudinal compressive stress into respective channels of the p-MOSFETs.
10. The CMOS device of claim 9 , wherein the silicon germanium stressors comprise raised epitaxial layers deposited selectively on top of the respective source and drain regions of the p-MOSFETs in the surface semiconductor layer, said respective source and drain regions of the p-MOSFETs comprising silicon.
11. The CMOS device of claim 1 , wherein the stressed buried structure comprises a stressed buried insulator structure.
12. A CMOS device comprising n-channel MOSFETs (n-MOSFETs) and p-channel MOSFETs (p-MOSFETs); the n-MOSFETs and p-MOSFETs being formed in respective first regions and second regions of a surface semiconductor layer overlying a stressed buried structure; the n-MOSFETs having shallow trench isolation structures formed at the ends of their respective source and drain regions, the shallow trench isolation structures being sufficiently deep to penetrate through an entire depth of the stressed buried structure thereby permitting elastic edge relaxation of the stressed buried structure underlying the first regions occupied by the n-MOSFETs, inducing longitudinal tensile strain in channels of the n-MOSFETs, and the p-MOSFETs having trench isolation structures formed at ends of their respective source and drain regions sufficiently far from their respective channel regions so as to avoid inducing a strain greater than 200 megaPascal in respective channels of the p-MOSFETs by edge relaxation of the stressed buried structure.
13. The CMOS device of claim 12 , wherein the stressed buried structure comprises a layer of compressively stressed silicon germanium underlying a layer of silicon oxide.
14. The CMOS device of claim 12 , wherein the surface semiconductor layer comprises a silicon layer.
15. The CMOS device of claim 13 , wherein the surface semiconductor layer comprises a silicon layer.
16. The CMOS device of claim 12 , wherein the surface semiconductor layer comprises a germanium layer.
17. The CMOS device of claim 13 , wherein the surface semiconductor layer comprises a germanium layer.
18. The CMOS device of claim 12 , wherein the surface semiconductor layer comprises a silicon germanium alloy layer.
19. The CMOS device of claim 13 , wherein the surface semiconductor layer comprises a silicon germanium alloy layer.
20. The CMOS device of claim 13 , further comprising silicon germanium stressors in respective source and drain regions of the p-MOSFETs, said silicon germanium stressors introducing longitudinal compressive stress into the respective channels of the p-MOSFETs.
21. The CMOS device of claim 20 , wherein the silicon germanium stressors comprise raised epitaxial layers deposited selectively on top of the respective source and drain regions of the p-MOSFETs in the surface semiconductor layer, said respective source and drain regions of the p-MOSFETs comprising silicon.
22. The CMOS device of claim 12 , wherein the stressed buried structure comprises a stressed buried insulator structure.