Semiconductor structures and fabrication methods thereof

1. A method for fabricating a semiconductor structure, comprising:

providing a substrate, including a first region and a second region;

forming a plurality of first gate structures on the first region of the substrate, a plurality of second gate structures on the second region of the substrate, and a first stress layer in the substrate on both sides of each first gate structure;

forming a first-region mask layer on the first stress layer;

forming a second stress layer in the substrate on both sides of each second gate structure using the first-region mask layer as a mask;

forming a contact-hole etch stop layer on the first stress layer and on the second stress layer;

forming a plurality of first contact holes on the first stress layer and a plurality of second contact holes on the second stress layer, wherein the contact-hole etch stop layer formed on the first stress layer is exposed at a bottom of each first contact hole, and the contact-hole etch stop layer formed on the second stress layer is exposed at a bottom of each second contact hole;

removing at least a portion of the contact-hole etch stop layer exposed at the bottom of each first contact hole, wherein a sum of a thickness of a remaining portion of the contact-hole etch stop layer and a thickness of the first-region mask layer equals at the bottom of each first contact hole approximately to a thickness of the contact-hole etch stop layer at the bottom of each second contact hole; and

removing the first-region mask layer at the bottom of each first contact hole and the contact-hole etch stop layer at the bottom of each second contact hole to expose the first stress layer and the second stress layer, respectively.

2. The method according to claim 1 , wherein:

the thinning down process includes dry etching.

3. The method according to claim 1 , wherein:

a thickness of the at least a portion of the contact-hole etch stop layer removed is in a range of approximately 30 Å to 200 Å.

4. The method according to claim 1 , wherein:

the contact-hole etch stop layer exposed at the bottom of each first contact hole is fully removed.

5. The method according to claim 4 , wherein:

the contact-hole etch stop layer exposed at the bottom of each first contact hole and a top portion of the first-region mask layer formed at the bottom of each first contact hole are removed.

6. The method according to claim 1 , wherein:

the first-region mask layer at the bottom of each first contact hole and the contact-hole etch stop layer at the bottom of each second contact hole to expose the first stress layer and the second stress layer is removed, respectively, after removing at least a portion of the contact-hole etch stop layer exposed at the bottom of each first contact hole.

7. A method for fabricating a semiconductor structure, comprising:

providing a substrate, including a first region and a second region;

forming a plurality of first gate structures on the first region of the substrate, a plurality of second gate structures on the second region of the substrate, and a first stress layer in the substrate on both sides of each first gate structure;

forming a first-region mask layer on the first stress layer and on the first stress layer;

forming a second stress layer in the substrate on both sides of each second gate structure using the first-region mask layer as a mask;

forming a contact-hole etch stop layer on the first stress layer and on the second stress layer;

forming a plurality of first contact holes on the first stress layer and a plurality of second contact holes on the second stress layer, wherein the contact-hole etch stop layer formed on the first stress layer is exposed at a bottom of each first contact hole, and the contact-hole etch stop layer formed on the second stress layer is exposed at a bottom of each second contact hole;

removing at least a portion of the contact-hole etch stop layer exposed at the bottom of each first contact hole; and

removing the first-region mask layer at the bottom of each first contact hole and the contact-hole etch stop layer at the bottom of each second contact hole to expose the first stress layer and the second stress layer, respectively wherein removing the at least a portion of the contact-hole etch stop layer exposed at the bottom of each first contact hole includes:

forming a protection layer on the second region of the substrate;

performing a thinning down process along a depth direction of each first contact hole to remove the at least a portion of the contact-hole etch stop layer exposed at the bottom of each first contact hole; and

removing the protection layer to expose the contact-hole etch stop layer at the bottom of each second contact hole.

8. The method according to claim 7 , wherein:

the protection layer fills up each second contact hole.

9. The method according to claim 7 , wherein:

the protection layer has a structure including one or more of a photoresist layer, an organic dielectric layer, and a bottom anti-reflection layer.

10. The method according to claim 7 , wherein:

at least one of the first-region mask layer and the contact-hole etch stop layer is made of SiN x .

11. The method according to claim 10 , wherein parameters of the thinning down process include:

an etch gas including CH 2 F 2 , O 2 , and CF 4 ;

a flow rate of CH 2 F 2 in a range of approximately 8 sccm to 50 sccm;

a flow rate of O 2 in a range of approximately 2 sccm to 30 sccm;

a flow rate of CF4 in a range of approximately 30 sccm to 200 sccm;

a radio frequency (RF) power in a range of approximately 100 W to 1000 W;

a voltage in a range of approximately 30 V to 500 V;

an etch time in a range of approximately 4 s to 500 s; and

a pressure in a range of approximately 10 mTorr to 2000 mTorr.

12. The method according to claim 7 , wherein:

the protection layer is removed through dry etching.

13. The method according to claim 7 , after performing the thinning down process and prior to removing the protection layer, further including:

performing a contact implantation process on the first stress layer along the depth direction of each first contact hole using the protection layer as a mask.

14. The method according to claim 13 , wherein:

a plurality of transistors formed on the first region of the substrate are P-type metal-oxide-semiconductor (PMOS) transistors;

a plurality of transistors formed on the second region of the substrate are N-type metal-oxide-semiconductor (NMOS) transistors; and

process parameters of the contact implantation process include:

an implantation energy in a range of approximately 1 keV to 50 keV; and

an implantation dose in a range of approximately 1.0E14 atom/cm 2 to 1.0E16 atom/cm 2 .

15. The method according to claim 7 , further including:

forming a first plug in each first contact hole and a second plug in each second contact hole.

16. The method according to claim 7 , wherein:

the thinning down process includes dry etching.

17. The method according to claim 7 , wherein:

a thickness of the at least a portion of the contact-hole etch stop layer removed is in a range of approximately 30 Å to 200 Å.

18. The method according to claim 7 , wherein:

the contact-hole etch stop layer exposed at the bottom of each first contact hole is fully removed.

19. The method according to claim 18 , wherein:

the contact-hole etch stop layer exposed at the bottom of each first contact hole and a top portion of the first-region mask layer formed at the bottom of each first contact hole are removed.