Phase and frequency detection method and circuit

1. An apparatus comprising:

a first circuit comprising a first edge-triggered flip-flop, a first logic circuit, a first delay circuit, and a first inverter, wherein the first edge-triggered flip-flop is configured to receive a first input pulse and to generate a first output pulse; and

a second circuit comprising a second edge-triggered flip-flop, a second logic circuit, and a second delay circuit, wherein the second edge-triggered flip-flop is configured to receive a second input pulse and to generate a second output pulse,

wherein a first output of the first edge-triggered flip-flop is coupled to an input of the inverter, and an output of the inverter is coupled to a first input of the first logic circuit and to the second delay circuit,

wherein a second output of the second edge-triggered flip-flop is coupled to a first input of the second logic circuit and to the first delay circuit,

wherein an output of the first delay circuit is coupled to a second input of the first logic circuit and an output of the first logic circuit is coupled to a first reset input of the first edge-triggered flip-flop,

wherein an output of the second delay circuit is coupled to a second input of the second logic circuit and an output of the second logic circuit is coupled to a second reset input of the second edge-triggered flip-flop,

wherein the second output pulse has a second falling edge carrying first information related to a first rising edge of the first input pulse, and

wherein a first falling edge of the first output pulse carries second information related to a second rising edge of the second input pulse.

2. The apparatus of claim 1 , wherein the first circuit is configured to generate the first output pulse having a first falling edge triggered by a first rising edge of the first input pulse.

3. The apparatus of claim 1 , wherein the second circuit is configured to generate the second output pulse having a second rising edge carrying the second information related to the second rising edge of the second input pulse.

4. The apparatus of claim 1 , wherein the first logic circuit comprises a first AND logic circuit, and wherein the first information includes a second delay time of the second delay circuit.

5. The apparatus of claim 1 , wherein the second logic circuit comprises a second AND logic circuit, and wherein the second information includes a first delay time of the first delay circuit.

6. A method of phase detecting, the method comprising:

receiving, by a first flip-flop of a first circuit, a first input pulse;

generating, by the first flip-flop of the first circuit, a first output pulse;

inverting with an inverter the first output pulse and delaying the inverted first output pulse with a first delay circuit;

receiving, by a second flip-flop of a second circuit, a second input pulse;

generating, by the second flip-flop of the second circuit, a second output pulse; and

delaying the second output pulse with a second delay circuit,

wherein the first flip-flop is configured to reset based on an output of a first logic circuit with an output of the inverter coupled to a first input of the first logic circuit and an output of the second delay circuit coupled to a second input of the first logic circuit,

wherein the second flip-flop is configured to be reset based on an output of a second logic circuit with an output of the second flip-flop coupled to a first input of the second logic circuit and an output of the first delay circuit coupled to a second input of the second logic circuit,

wherein generating the second output pulse comprises generating the second output pulse having a second falling edge carrying first information related to a first rising edge of the first input pulse, and

wherein generating the first output pulse comprises generating the first output pulse having a first falling edge carrying second information related to a second rising edge of the second input pulse.

7. The method of claim 6 , wherein generating the first output pulse comprises generating the first output pulse having a first falling edge triggered by a first rising edge of the first input pulse.

8. The method of claim 6 , wherein generating the second output pulse comprises generating the second output pulse having a second rising edge carrying information related to the second rising edge of the second input pulse.

9. The method of claim 6 , wherein the first logic circuit comprises a first AND logic circuit, wherein the second logic circuit comprises a second AND logic circuit, and wherein the first information includes a second delay time of the second delay circuit.

10. The method of claim 9 , wherein the second information includes a first delay time of the first delay circuit.

11. A communication device comprising:

a phased-lock loop (PLL) circuit configured to generate clock signals;

the PLL circuit comprising a phase and frequency detection (PFD) circuit comprising:

a first circuit comprising a first edge-triggered flip-flop, a first logic AND circuit, a first delay circuit, and a second delay circuit, wherein the first circuit is configured to receive a first input pulse and to generate a first output pulse; and

a second circuit comprising a second edge-triggered flip-flop, a second logic AND circuit, a third delay circuit, and a fourth delay circuit, wherein the second circuit is configured to receive a second input pulse and to generate a second output pulse,

wherein:

a first output of the first edge-triggered flip-flop is coupled to an input of the first delay circuit, and an output of the first delay circuit is coupled to a first input of the first logic AND circuit and to an input of the fourth delay circuit,

a second output of the second edge-triggered flip-flop is coupled to an input of the third delay circuit, and an output of the third delay circuit is coupled to a first input of the second logic AND circuit and to an input of the second delay circuit,

an output of the second delay circuit is coupled to a second input of the first logic AND circuit and an output of the first logic AND circuit is coupled to a first reset input of the first edge-triggered flip-flop,

an output of the fourth delay circuit is coupled to a second input of the second logic AND circuit and an output of the second logic AND circuit is coupled to a second reset input of the second edge-triggered flip-flop,

a second falling edge of the second output pulse carries first information related to a first rising edge of the first input pulse, and

a first falling edge of the first output pulse carries second information related to a second rising edge of the second input pulse.

12. The communication device of claim 11 , wherein the first circuit is configured to generate the first output pulse having a first rising edge approximately coinciding with a first rising edge of the first input pulse; and wherein the second circuit is configured to generate the second output pulse having a second rising edge triggered by the second rising edge of the second input pulse.