Fan-out semiconductor package

1. A fan-out semiconductor package comprising:

a connection member including an insulating layer and a redistribution layer;

a semiconductor chip disposed on the connection member;

an encapsulant encapsulating the semiconductor chip; and

an electromagnetic wave shielding layer disposed on the semiconductor chip, and including a plurality of degassing holes,

wherein the electromagnetic wave shielding layer includes a first region and a second region in which densities of the plurality of degassing holes are different from each other, the first region having a density of the degassing holes higher than a density of the degassing holes in the second region.

2. The fan-out semiconductor package according to claim 1 , wherein the second region is disposed in a region corresponding to the semiconductor chip.

3. The fan-out semiconductor package according to claim 1 , wherein the electromagnetic wave shielding layer further comprises a third region in which the degassing holes are not formed.

4. The fan-out semiconductor package according to claim 3 , wherein the third region is disposed in a region corresponding to the semiconductor chip.

5. The fan-out semiconductor package according to claim 3 , further comprising a core member having a through hole in which the semiconductor chip is disposed,

wherein the third region is disposed in a region corresponding to the core member.

6. The fan-out semiconductor package according to claim 5 , wherein the core member comprises a metal layer covering at least a wall surface of the through hole.

7. The fan-out semiconductor package according to claim 6 , wherein the metal layer extends from the wall surface of the through hole to one or more of an upper surface of the core member or a lower surface of the core member.

8. The fan-out semiconductor package according to claim 7 , wherein the metal layer of the core member and the electromagnetic wave shielding layer are connected by a conductive via penetrating through the encapsulant.

9. The fan-out semiconductor package according to claim 1 , further comprising a plurality of passive components disposed on the connection member.

10. The fan-out semiconductor package according to claim 9 , wherein the first region is disposed in a region corresponding to at least a portion of the plurality of passive components.

11. The fan-out semiconductor package according to claim 9 , wherein distances from upper surfaces of at least portions of the plurality of passive components to an upper surface of the encapsulant are different from each other, and a density of the plurality of degassing holes is higher in a region in which a distance to the upper surface of the encapsulant, is longer, among the different distances from the upper surfaces of the at least portions of the plurality of passive components to the upper surface of the encapsulant.

12. The fan-out semiconductor package according to claim 11 , wherein the electromagnetic wave shielding layer further comprises a third region in which the degassing holes are not formed, and the third region is disposed in a region in which a distance to the upper surface of the encapsulant, is shorter, among the different distances from the upper surfaces of the at least portions of the plurality of passive components to the upper surface of the encapsulant.

13. The fan-out semiconductor package according to claim 9 , wherein the plurality of passive components comprise a capacitor and an inductor, and a density of the degassing holes in a region corresponding to the capacitor is higher than a density of the degassing holes in a region corresponding to the inductor.

14. The fan-out semiconductor package according to claim 13 , wherein the electromagnetic wave shielding layer further comprises a third region in which the degassing holes are not formed, and the third region is disposed in a region corresponding to the inductor.

15. The fan-out semiconductor package according to claim 1 , wherein sizes of the degassing holes in the first region and the second region are equal to each other, and the number of the degassing holes per unit area in the first region is higher than that in the second region.

16. The fan-out semiconductor package according to claim 1 , wherein an average size of the plurality of degassing holes is less than or equal to 60 μm.

17. The fan-out semiconductor package according to claim 1 , wherein the electromagnetic wave shielding layer comprises a first layer and a second layer covering the first layer.

18. The fan-out semiconductor package according to claim 17 , wherein the first layer and the second layer are plating layers.

19. The fan-out semiconductor package according to claim 17 , wherein the second layer completely covers upper surfaces of the first layer and side surfaces of the first layer.

20. The fan-out semiconductor package according to claim 19 , wherein the electromagnetic wave shielding layer further comprises a seed layer completely covered by the first layer.

21. The fan-out semiconductor package according to claim 1 , further comprising a passivation layer covering the electromagnetic wave shielding layer.

22. The fan-out semiconductor package according to claim 21 , wherein portions of the passivation layer fill the plurality of degassing holes of the electromagnetic wave shielding layer.

23. The fan-out semiconductor package according to claim 22 , wherein the portions of the passivation layer filling the plurality of degassing holes of the electromagnetic wave shielding layer are in direct contact with the encapsulant.

24. The fan-out semiconductor package according to claim 1 , wherein the electromagnetic wave shielding layer extends continuously between edges of the fan-out semiconductor package.