IP Library Granted Patent US 10,304,750
Granted Patent B2
US 10,304,750 · App. 16/106,107 · Granted May 28, 2019

Package structure and its fabrication method

Inventor: Che-Wei Hsu (Hsinchu County, TW)
Assignee: PHOENIX & CORPORATION
H01L23/295H01L21/565H01L21/568H01L21/6835H01L23/3135H01L24/02H01L24/19H01L21/561H01L23/3128H01L24/29H01L24/32H01L24/73H01L24/83H01L24/92H01L2221/68345H01L2221/68359H01L2224/024H01L2224/02331H01L2224/02379H01L2224/02381H01L2224/04105H01L2224/12105H01L2224/214H01L2224/2929H01L2224/29387H01L2224/32225H01L2224/73267H01L2224/82039H01L2224/83005H01L2224/83191H01L2224/92244H01L2224/97H01L2924/1433
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Quick Facts
Patent No.
US 10,304,750
App. No.
16/106,107
Granted
May 28, 2019
Kind
B2
Abstract

A package structure is provided, which includes: a first polymer layer with a first surface; a second polymer layer with a second surface on the first polymer layer; a circuit device with opposing third and fourth surfaces, the circuit device disposed on the second polymer layer and with multiple metal pads on the fourth surface; a first high-filler dielectric layer enclosing the circuit device and the second polymer layer and covering the first polymer layer; a first conductive wiring formed on the first high-filler dielectric layer; a first conductive passage formed in the first high-filler dielectric layer and connecting the first conductive wiring to the metal pads; a second high-filler dielectric layer enclosing the first conductive wiring and covering the first high-filler dielectric layer; and a second conductive passage formed in the second high-filler dielectric layer and connecting the first conductive wiring to an external circuit.

Claims (34)

1. A package structure comprising:

a first polymer layer with a first surface;

a second polymer layer with a second surface on the first polymer layer;

a circuit device with a third surface and an opposite fourth surface, the circuit device disposed on the second polymer layer and with multiple metal pads on the fourth surface;

a first high-filler dielectric layer enclosing the circuit device and the second polymer layer and covering the first polymer layer;

a first conductive wiring formed on the first high-filler dielectric layer;

a first conductive passage formed in the first high-filler dielectric layer and connecting the first conductive wiring to the metal pad;

a second high-filler dielectric layer enclosing the first conductive wiring and covering the first high-filler dielectric layer; and

a second conductive passage formed in the second high-filler dielectric layer and connecting the first conductive wiring to an external circuit;

wherein the first surface is larger than the second surface, and the second surface and the third surface are identical in area size.

2. The package structure of claim 1 , wherein the first polymer layer comprises epoxy-based resin, and the second polymer layer comprises epoxy-based resin.

3. The package structure of claim 1 , wherein the first high-filler dielectric layer comprises a first molding compound, and the second high-filler dielectric layer comprises a second molding compound.

4. The package structure of claim 1 , wherein the circuit device comprises a semiconductor chip or an electronic component.

5. The package structure of claim 1 , further comprising:

a second conductive wiring formed on the second conductive passage and the second high-filler dielectric layer;

a protective layer enclosing the second conductive wiring and covering the second high-filler dielectric layer; and

a third conductive passage formed in the protective layer and connecting the second conductive wiring to an external circuit.

6. The package structure of claim 5 , wherein the second conductive passage comprises a metal pillar.

7. A method for fabricating a package structure, comprising steps of:

(A) providing a carrier and a plurality of circuit devices, the carrier having a first surface, each of the circuit devices having a second surface and an opposite third surface, and each of the circuit devices with multiple metal pads on the third surface;

(B) forming a first polymer layer on the carrier, while enabling the first polymer layer to completely cover the first surface of the carrier;

(C) forming a second polymer layer on all of the circuit devices, while enabling the second polymer layer to completely cover the second surfaces of the circuit devices;

(D) arranging the circuit devices on the carrier, while enabling the second polymer layer to be adhered to the first polymer layer;

(E) forming a first high-filler dielectric layer on the carrier, while enabling the first high-filler dielectric layer to cover the circuit devices;

(F) forming a first conductive passage in the first high-filler dielectric layer, and forming a first conductive wiring on the first conductive passage, while enabling the first conductive passage to connect the first conductive wiring to the metal pad;

(G) forming a second high-filler dielectric layer on the first high-filler dielectric layer, while enabling the second high-filler dielectric layer to enclose the first conductive wiring and cover the first high-filler dielectric layer;

(H) forming a second conductive passage in the second high-filler dielectric layer, while enabling the second conductive passage to be connected to the first conductive wiring;

(I) removing the carrier to get a semi-finished package structure containing the circuit devices; and

(F) dividing the semi-finished package structure into a plurality of package structures, while enabling each of the package structures has one of the circuit devices.

8. The method of claim 7 , wherein the first polymer layer is formed by pressing or coating and then baked in step (B).

9. The method of claim 7 , wherein the second polymer layer is formed by pressing, coating or printing and then baked in step (C).

10. The method of claim 7 , wherein the first conductive passage is formed by following steps:

laser drilling a through opening in the first high-filler dielectric layer on the metal pads of the circuit devices; and

filling up the through opening with conducting material by electroplating.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2020
From: PHOENIX & CORPORATION
To: PHOENIX PIONEER TECHNOLOGY CO., LTD.
Reel/Frame 053010/0360 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2018
From: HSU, CHE-WEI
To: PHOENIX & CORPORATION
Reel/Frame 046637/0930 →
Priority Claims (1)
TW 106128487 A · Aug 22, 2017 · national
Continuity (1)
Related Publication 20190067140A1 · Feb 28, 2019