Semiconductor structure and fabrication method thereof
Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate including a plurality of fins on a semiconductor substrate; forming a gate layer across the fins; forming a P-type doped epitaxial layer in the fins at both sides of the gate layer in a PMOS region of the semiconductor substrate; forming an N-region mask layer on top and sidewall surfaces of the fins in the NMOS region and covering the P-type doped epitaxial layer; forming an N-region trench; forming an N-type doped epitaxial layer by filling the N-region trench; forming an interlayer dielectric layer over the semiconductor substrate; forming a contact opening to expose the P-type doped epitaxial layer and the N-type doped epitaxial layer; and performing an N-type dopant segregated Schottky (DSS) doping process on a portion of the N-type doped epitaxial layer exposed by the contact opening.
1. A method for fabricating a semiconductor structure, comprising:
providing a base substrate including a plurality of fins on a semiconductor substrate having a PMOS region and an NMOS region;
forming a gate layer across the fins by covering portions of top and side surfaces of the fins
forming a P-type doped epitaxial layer in the fins at both sides of the gate layer in the PMOS region;
forming an N-region mask layer on top and side surfaces of the fins in the NMOS region and covering the P-type doped epitaxial layer;
removing a portion of the N-region mask layer on top surfaces of the fins at both sides of the gate layer and a partial thickness of the fins in the NMOS region, wherein remaining fins in the NMOS region and the N-region mask layer form an N-region trench;
forming an N-type doped epitaxial layer by filling the N-region trench;
forming an interlayer dielectric layer covering the gate layer, the P-type doped epitaxial layer and the N-type doped epitaxial layer on the semiconductor substrate;
etching the interlayer dielectric layer at both sides of the gate layer to form a contact opening to expose the N-type doped epitaxial layer and a remaining portion of the N-region mask layer; and
performing an N-type dopant segregated Schottky (DSS) doping process on a portion of the N-type doped epitaxial layer exposed by the contact opening using the remaining portion of the N-region mask layer as a mask.
2. The method according to claim 1 , wherein:
doping ions of the N-type dopant segregated Schottky (DSS) doping process include at least one of P ions, As ions and Sb ions.
3. The method according to claim 2 , wherein:
the N-type dopant segregated Schottky (DSS) doping process is an ion implantation process;
an implanting energy of the ion implantation process is in a range of approximately 100 eV-1 keV; and
an implanting dosage of the ion implantation process is in a range of approximately 1E14 atom/cm 2 -1E16 atom/cm 2 .
4. The method according to claim 1 , before forming the gate layer, further comprising:
forming shallow trench isolation (STI) structures on the semiconductor substrate, wherein:
top surfaces of the shallow trench isolation (STI) structures are lower than top surfaces of the fins; and
after removing the partial thickness of the fins in the NMOS region, a height difference between top surfaces of the remaining fins in the NMOS region and top surfaces of the shallow trench isolation structures is in a range approximately from −3 nm to 3 nm.
5. The method according to claim 1 , wherein:
the N-region mask layer is made of one of silicon nitride, silicon oxide, boron nitride, silicon carbonitride, silicon boron oxycarbonitride, and silicon oxynitride.
6. The method according to claim 1 , wherein forming the P-type doped epitaxial layer in the fins at both sides of the gate layer in the PMOS region comprises:
forming a P-region mask layer on top and sidewall surfaces of the fins in the PMOS region;
removing a portion of the P-region mask layer on top surfaces of the fins at both sides of the gate layer in the PMOS region and a partial thickness of the fins in the PMOS region, wherein remaining fins in the PMOS region and the P-region mask layer form a P-region trench; and
forming the P-type doped epitaxial layer by filling the P-region trench.
7. The method according to claim 6 , before forming the gate layer, further comprising:
forming shallow trench isolation (STI) structures on the semiconductor substrate, wherein:
top surfaces of the shallow trench isolation (STI) structures are lower than top surfaces of the fins; and
after removing the partial thickness of the fins in the PMOS region, a height difference between top surfaces of remaining fins in the PMOS region and top surfaces of the shallow trench isolation structures is in a range approximately from −3 nm to 3 nm.
8. The method according to claim 6 , after forming the P-region trench and before forming the P-type doped epitaxial layer by filling the P-region trench, further comprising:
performing a first pull-back process on portions of the P-region mask layer on sidewall surfaces of the P-region trench.
9. The method according to claim 8 , wherein:
before performing the first pull-back process, a thickness of the P-region mask layer is in a range of approximately 5 nm-10 nm; and
after performing the first pull-back process, a thickness of the P-region mask layer is in a range of approximately 3 nm-7 nm.
10. A method for fabricating a semiconductor structure, comprising:
providing a base substrate including a plurality of fins on a semiconductor substrate having a PMOS region and an NMOS region;
forming a gate layer across the fins by covering portions of top and side surfaces of the fins
forming a P-type doped epitaxial layer in the fins at both sides of the gate layer in the PMOS region;
forming an N-region mask layer on top and side surfaces of the fins in the NMOS region and covering the P-type doped epitaxial layer;
performing a second pull-back process on portions of the N-region mask layer on sidewall surfaces of the N-region trench;
removing a portion of the N-region mask layer on top surfaces of the fins at both sides of the gate layer and a partial thickness of the fins in the NMOS region, wherein remaining fins in the NMOS region and the N-region mask layer form an N-region trench;
forming an N-type doped epitaxial layer by filling the N-region trench;
forming an interlayer dielectric layer covering the gate layer, the P-type doped epitaxial layer and the N-type doped epitaxial layer on the semiconductor substrate;
etching the interlayer dielectric layer at both sides of the gate layer to form a contact opening to expose the P-type doped epitaxial layer and the N-type doped epitaxial layer; and
performing an N-type dopant segregated Schottky (DSS) doping process on a portion of the N-type doped epitaxial layer exposed by the contact opening.
11. The method according to claim 10 , wherein:
before performing the second pull-back process, a thickness of the N-region mask layer is in a range of approximately 8 nm-16 nm; and
after performing the second pull-back process, a thickness of the N-region mask layer is in a range of approximately 4 nm-10 nm.
12. The method according to claim 10 , wherein:
the second pull-back process is one of a dry etching process and a wet etching process.
13. The method according to claim 1 , after performing the N-type dopant segregated Schottky doping process, further comprising:
removing the N-region mask layer;
forming a metal silicide layer on a portion of the P-type doped epitaxial layer and a portion of the N-type doped epitaxial layer exposed by the contact opening; and
forming a contact plug electrically contacting with the P-type doped epitaxial layer and the N-type doped epitaxial layer by filling a conductive material into the contact opening.
14. The method according to claim 10 , wherein:
doping ions of the N-type dopant segregated Schottky (DSS) doping process include at least one of P ions, As ions and Sb ions.
15. The method according to claim 14 , wherein:
the N-type dopant segregated Schottky (DSS) doping process is an ion implantation process;
an implanting energy of the ion implantation process is in a range of approximately 100 eV-1 keV; and
an implanting dosage of the ion implantation process is in a range of approximately 1E14 atom/cm 2 -1E16 atom/cm 2 .
16. The method according to claim 10 , before forming the gate layer, further comprising:
forming shallow trench isolation (STI) structures on the semiconductor substrate, wherein:
top surfaces of the shallow trench isolation (STI) structures are lower than top surfaces of the fins; and
after removing the partial thickness of the fins in the NMOS region, a height difference between top surfaces of the remaining fins in the NMOS region and top surfaces of the shallow trench isolation structures is in a range approximately from −3 nm to 3 nm.
17. The method according to claim 10 , wherein:
the N-region mask layer is made of one of silicon nitride, silicon oxide, boron nitride, silicon carbonitride, silicon boron oxycarbonitride, and silicon oxynitride.
18. The method according to claim 10 , wherein forming the P-type doped epitaxial layer in the fins at both sides of the gate layer in the PMOS region comprises:
forming a P-region mask layer on top and sidewall surfaces of the fins in the PMOS region;
removing a portion of the P-region mask layer on top surfaces of the fins at both sides of the gate layer in the PMOS region and a partial thickness of the fins in the PMOS region, wherein remaining fins in the PMOS region and the P-region mask layer form a P-region trench; and
forming the P-type doped epitaxial layer by filling the P-region trench.
19. The method according to claim 18 , before forming the gate layer, further comprising:
forming shallow trench isolation (STI) structures on the semiconductor substrate, wherein:
top surfaces of the shallow trench isolation (STI) structures are lower than top surfaces of the fins; and
after removing the partial thickness of the fins in the PMOS region, a height difference between top surfaces of remaining fins in the PMOS region and top surfaces of the shallow trench isolation structures is in a range approximately from −3 nm to 3 nm.
20. The method according to claim 18 , after forming the P-region trench and before forming the P-type doped epitaxial layer by filling the P-region trench, further comprising:
performing a first pull-back process on portions of the P-region mask layer on sidewall surfaces of the P-region trench.