Semiconductor device

1. A semiconductor device comprising:

an interlayer insulation layer on a substrate;

a via plug in the interlayer insulation layer, the via plug having opposite first and second via sidewalls;

a first wiring line in the interlayer insulation layer, the first wiring line coupled with the via plug and having a first wiring sidewall adjacent to the first via sidewall and a second wiring sidewall opposite to the first wiring sidewall and adjacent to the second via sidewall;

a first via insulation liner covering the first via sidewall;

a first wiring insulation liner covering the first wiring sidewall;

a first via air-gap region between the first via insulation liner and the interlayer insulation layer, the first via air-gap region exposing the first via insulation liner to the interlayer insulation layer; and

a first wiring air-gap region between the first wiring insulation liner and the interlayer insulation layer, the first wiring air-gap region exposing the first wiring insulation liner to the interlayer insulation layer;

wherein the first via sidewall and the second wiring sidewall are misaligned with each other.

2. The semiconductor device according to claim 1 ,

wherein the first wiring air-gap region does not vertically overlap with the first via air-gap region, and

wherein the first wiring insulation liner is separated from the interlayer insulation layer by the first wiring air-gap region.

3. The semiconductor device according to claim 2 , further comprising:

a connection air-gap region connecting the first wiring air-gap region and the first via air-gap region and exposing a portion of a lower surface of the first wiring line to the interlayer insulation layer.

4. The semiconductor device according to claim 3 , wherein a vertical width of the connection air-gap region is smaller than a horizontal width of the first wiring air-gap region.

5. The semiconductor device according to claim 1 , further comprising:

an etch stop layer between the interlayer insulating layer and the substrate,

wherein the first via air-gap region extends between the etch stop layer and the via plug, and

wherein a portion of an upper surface and a sidewall of the etch stop layer is exposed to the first via air-gap region.

6. The semiconductor device according to claim 1 , wherein the second via sidewall and the second wiring sidewall are directly connected to each other and extend in a line.

7. The semiconductor device according to claim 6 , further comprising:

a second via air-gap region between the second via sidewall and the interlayer insulation layer; and

a second wiring air-gap region between the second wiring sidewall and the interlayer insulation layer,

wherein the second via air-gap region and the second wiring air-gap region are directly connected with each other.

8. The semiconductor device according to claim 1 , wherein a portion of a lower surface of the first wiring line contacts the interlayer insulation layer between the first via air-gap region and the first wiring air-gap region.

9. The semiconductor device according to claim 1 ,

wherein the interlayer insulation layer is exposed by the first via air-gap region to the first via insulation liner, and

wherein the interlayer insulation layer is exposed by the first wiring air-gap region to the first wiring line.

10. The semiconductor device according to claim 1 , further comprising:

a second via insulation liner opposite to the first via insulation liner with the first via air-gap region therebetween; and

a second wiring insulation liner opposite to the first wiring insulation liner with the first wiring air-gap region therebetween.

11. The semiconductor device according to claim 1 , further comprising:

a damaged region in a portion of the interlayer insulation layer adjacent to the via plug and the first wiring line,

wherein a carbon concentration in the damaged region is lower than a carbon concentration in the interlayer insulation layer.

12. The semiconductor device according to claim 1 , wherein a width of an upper portion of the first via insulation liner is smaller than a width of a lower portion of the first via insulation liner.

13. The semiconductor device according to claim 1 , further comprising a protection layer covering an upper surface of the first wiring line.

14. The semiconductor device according to claim 1 , further comprising a lower conductive pattern in the interlayer insulation layer below the via plug, the lower conductive pattern contacting the via plug,

wherein the first via air-gap region exposes a portion of an upper surface of the lower conductive pattern to the first air-gap region and/or to the first via insulation liner.

15. The semiconductor device according to claim 1 , further comprising:

a second wiring line in the interlayer insulation layer, the second wiring line being spaced apart from the first wiring line;

a second wiring insulation liner covering a sidewall of the second wiring line; and

a second wiring air-gap region between the second wiring insulation liner and the interlayer insulation layer, the second wiring air-gap region exposing the second wiring insulation liner to the interlayer insulation layer.

16. The semiconductor device according to claim 15 , wherein the second air-gap region extends below the second wiring line to expose a lower surface of the second air-gap region to the interlayer insulation layer.

17. A semiconductor device comprising:

an interlayer insulation layer on a semiconductor substrate;

a via plug and a wiring line on the via plug, in the interlayer insulation layer, the via plug and the wiring line coupled with each other and forming a stepped structure;

a first insulation layer covering a sidewall of the via plug and a sidewall of the wiring line;

a second insulation layer covering a sidewall of a portion of the first insulation layer covering the sidewall of the via plug, the second insulation layer comprising a different material from the first insulation layer;

an air-gap region between the interlayer insulation layer and the wiring line, the air-gap region exposing the first insulation layer to the interlayer insulation layer; and

a damaged region in a portion of the interlayer insulation layer adjacent to the air-gap region and the second insulation layer,

wherein a first carbon concentration in the damaged region is lower than a second carbon concentration in the interlayer insulation layer and is higher than a third carbon concentration in the second insulation layer.

18. The semiconductor device according to claim 17 , wherein a first oxygen concentration in the damaged region is higher than a second oxygen concentration in the interlayer insulation layer and is lower than a third oxygen concentration in the second insulation layer.

19. A semiconductor device comprising:

an interlayer insulation layer on a semiconductor substrate;

a via plug and a wiring line on the via plug, in the interlayer insulation layer, the via plug and the wiring line coupled with each other and forming a stepped structure;

a first air-gap region between the interlayer insulation layer and the via plug; and

a second air-gap region between the interlayer insulation layer and the wiring line;

wherein the first air-gap region and the second air-gap region are not vertically overlapped with each other in a plan view of the semiconductor device.

20. The semiconductor device according to claim 19 , further comprising:

a connection air-gap region connecting between the first air-gap region and the second air-gap region, the connection air-gap region exposing a lower surface of the wiring line to the interlayer insulation layer,

wherein a vertical width of the connection air-gap region is smaller than a horizontal width of the first air-gap region.