Capacitive-coupled non-volatile thin-film transistor strings in three dimensional arrays
Multi-gate NOR flash thin-film transistor (TFT) string arrays are organized as three dimensional stacks of active strips. Each active strip includes a shared source sublayer and a shared drain sublayer that is connected to substrate circuits. Data storage in the active strip is provided by charge-storage elements between the active strip and a multiplicity of control gates provided by adjacent local word-lines. The parasitic capacitance of each active strip is used to eliminate hard-wire ground connection to the shared source making it a semi-floating, or virtual source. Pre-charge voltages temporarily supplied from the substrate through a single port per active strip provide the appropriate voltages on the source and drain required during read, program, program-inhibit and erase operations. TFTs on multiple active strips can be pre-charged separately and then read, programmed or erased together in a massively parallel operation.
1. A memory structure, comprising:
a semiconductor substrate having a substantially planar surface, wherein the semiconductor substrate has circuitry formed therein;
a first stack of active strips and a second stack of active strips formed over the surface of the semiconductor substrate and separated by a predetermined distance along a first direction, wherein each stack of active strips comprises two or more active strips provided one on top of another on two or more isolated planes and being substantially aligned lengthwise with each other along a second direction substantially parallel to the planar surface, and wherein each active strip comprises a first semiconductor layer of a first conductivity type provided between a second semiconductor layer and a third semiconductor layer each of a second conductivity type, the first, second and third semiconductor layers each comprise polysilicon or silicon germanium;
a charge-trapping material; and
a plurality of conductors each extending lengthwise along a third direction that is substantially perpendicular to the planar surface, each conductor being within a group of the conductors that are provided between the first stack of active strips and the second stack of active strips and separated from each stack of active strips by the charge-trapping material, thereby forming in each active strip at least one NOR string, each NOR string including a plurality of thin-film transistors that are formed out of the first, the second and the third semiconductor layers of the active strip and their adjacent charge-trapping material and the conductors within the group, wherein (a) the first, second and third semiconductor layers in each active strip provide, respectively, channel, source and drain regions of the thin-film transistors, (b) the thin-film transistors of each active strip sharing source and drain regions in common, (c) adjacent first and second NOR strings are formed on opposite sides of each active strip, with each thin-film transistor of the first NOR strings being adjacent to a corresponding thin-film transistor of the second NOR string, the channel regions of the corresponding thin-film transistors being separated by an insulating spine.
2. The memory structure of claim 1 , further comprising a second plurality of conductors formed along the first direction, the second plurality of conductors each connecting a portion of the circuitry at the surface of the semiconductor substrate to selected ones of the first plurality of conductors that serve as gate electrodes of the thin-film storage transistors.
3. The memory structure of claim 2 , wherein the second plurality of conductors are formed between the planar surface and the active strips, the memory structure further comprising a third plurality of conductors formed above the active strips along the first direction, the third plurality of conductors each connecting a portion of the circuitry at the surface of the semiconductor substrate to selected ones of the first plurality of conductors that serve as gate electrodes of the thin-film storage transistors.
4. The memory structure of claim 3 , wherein the selected ones of the first plurality of conductors that are connected to the second plurality of conductors and the selected ones of the first plurality of conductors that are connected to the third plurality of conductors are provided on opposite sides of an active strip.
5. The memory structure of claim 3 , wherein each thin-film transistor is associated with a numeric address, wherein the thin-film storage transistors associated with even addresses are connected to the second plurality of conductors and wherein the thin-film storage transistors associated with odd addresses are connected to the third plurality of conductors.
6. The memory structure of claim 1 , wherein each active strip further comprises at least one metallic layer that is in electrical contact with, and in substantial alignment lengthwise with, one or both of the second semiconductor layer and the third semiconductor layer.
7. The memory structure of claim 1 , further comprising a dopant diffusion-blocking layers between the first semiconductor layer and the second semiconductor layer and between the second semiconductor layer and the third semiconductor layer.
8. The memory structure of claim 7 , wherein the dopant diffusion-blocking layer comprises a dielectric material that is less than three nanometers thick.
9. The memory structure of claim 1 , further comprising buried contact structures to connect one of the second and third semiconductor layers of each active strip to circuitry at the surface of the semiconductor substrate.
10. The memory structure of claim 1 , further comprising electrically conductive material providing shielding between thin film storage transistors on adjacent NOR strings.
11. The memory structure of claim 1 , wherein the channel region of each thin-film storage transistor is connected to the semiconductor substrate by a pillar of semiconductor material of the first conductivity type.