Device and method for supporting clock transfer of multiple clock domains
A device and a method for supporting clock transfer of multiple clock domains, where the device includes N phase frequency detectors, N filters, N clock reconstructors, and N clock domain interfaces, where N is an integer greater than or equal to two, the N clock domain interfaces are in a one-to-one correspondence with the N phase frequency detectors, the N filters, and the N clock reconstructors, the N phase frequency detectors are respectively connected to N clock sources, and at least two clock sources of the N clock sources are different. The foregoing device flexibly adapt to multiple different clock domains, implement that a single device simultaneously supports clock transfer of multiple clock domains, and flexibly satisfy user demands without adding or replacing devices.
1. A device for supporting clock transfer of a plurality of clock domains, comprising:
an i th phase frequency detector in N phase frequency detectors configured to:
receive a clock signal from a clock source coupled to the i th phase frequency detector; and
send i th phase difference information between a common reference clock signal and the clock signal to an i th filter in N filters corresponding to the i th phase frequency detector;
the i th filter being configured to:
receive the i th phase difference information from the i th phase frequency detector;
convert the i th phase difference information into i th frequency difference information; and
send the i th frequency difference information to an i th clock reconstructor in N clock reconstructors corresponding to the i th filter; and
the i th clock reconstructor being configured to:
receive the i th frequency difference information from the i th filter;
reconstruct an i th network timing clock in the device according to the common reference clock signal and the i th frequency difference information; and
send the i th network timing clock to an i th clock domain interface in N clock domain interfaces, the N phase frequency detectors respectively coupled to N clock sources, at least two clock sources of the N clock sources do not comprising a same clock source, the N clock domain interfaces comprising a one-to-one correspondence with the N phase frequency detectors, the N filters and the N clock reconstructors, the N comprising an integer greater than or equal to two, and the i comprising an integer satisfying a condition 1≤i≤N.
2. The device of claim 1 , further comprising an (N+1) th phase frequency detector coupled to an external clock source using an external synchronization interface and configured to:
receive a clock signal from the external clock source; and
send (N+1) th phase difference information between the clock signal from the external clock source and the common reference clock signal to a j th filter in the N filters,
the j th filter being configured to:
receive the (N+1) th phase difference information from the (N+1) th phase frequency detector;
convert the (N+1) th phase difference information into (N+1) th frequency difference information; and
send the (N+1) th frequency difference information to a j th clock reconstructor in the N clock reconstructors corresponding to the j th filter, and
the j th clock reconstructor being configured to:
receive the (N+1) th frequency difference information from the j th filter;
reconstruct an (N+1) th network timing clock in the device according to the common reference clock signal and the (N+1) th frequency difference information; and
send the (N+1) th network timing clock to a j th clock domain interface in the N clock domain interfaces, the j comprising an integer satisfying a condition 1≤j≤N.
3. The device of claim 2 , further comprising an (N+1) th clock reconstructor, a k th filter in the N filters being configured to send k th frequency difference information from the k th filter to the (N+1) th clock reconstructor, and the (N+1) th clock reconstructor being configured to:
receive the k th frequency difference information from the k th filter;
reconstruct a k th network timing clock in the device according to the k th frequency difference information; and
send the k th network timing clock to the external synchronization interface, the k comprising an integer satisfying a condition 1≤k≤N.
4. The device of claim 1 , further comprising an input selector coupled to the N phase frequency detectors and the N filters, the i th phase frequency detector being further configured to send the i th phase difference information to the input selector, and the input selector being configured to:
receive the i th phase difference information from the i th phase frequency detector; and
send, based on a correspondence between the i th phase frequency detector and the i th filter, the i th phase difference information to the i th filter.
5. The device of claim 4 , wherein the input selector is further configured to:
select M pieces of phase difference information of phase difference information received from the N phase frequency detectors when clock sources of the N clock domain interfaces correspond to M types of services, the M pieces of phase difference information comprising a one-to-one correspondence with the M types of services; and
send, based on a correspondence between the N phase frequency detectors and the N filters, corresponding phase difference information to each filter in the N filters, the M comprising an integer less than N.
6. The device of claim 1 , further comprising an output selector coupled to the N filters and the N clock reconstructors and, the i th filter being further configured to send the i th frequency difference information to the output selector, and the output selector being configured to:
receive the i th frequency difference information from the i th filter; and
send the i th frequency difference information to the i th clock reconstructor based on a correspondence between the i th filter and the i th clock reconstructor.
7. The device of claim 1 , further comprising a common reference clock generator coupled to the N phase frequency detectors and the N clock reconstructors and configured to:
generate the common reference clock signal before the i th phase difference information between the common reference clock signal and the clock signal is sent; and
send the common reference clock signal to the i th phase frequency detector and the i th clock reconstructor.
8. A method for supporting clock transfer of a plurality of clock domains, comprising:
receiving, by an i th phase frequency detector in N phase frequency detectors, a clock signal from a clock source coupled to the i th phase frequency detector;
sending, by the i th phase frequency detector, i th phase difference information between a common reference clock signal and the clock signal to an i th filter in N filters corresponding to the i th phase frequency detector;
receiving, by the i th filter, the i th phase difference information from the i th phase frequency detector;
converting, by the i th filter, the i th phase difference information into i th frequency difference information;
sending, by the i th filter, the i th frequency difference information to an i th clock reconstructor in N clock reconstructors corresponding to the i th filter;
receiving, by the i th clock reconstructor, the i th frequency difference information from the i th filter;
reconstructing, by the i th clock reconstructor, an i th network timing clock according to the common reference clock signal and the i th frequency difference information; and
sending, by the i th clock reconstructor, the i th network timing clock to an i th clock domain interface in N clock domain interfaces, the N comprising an integer greater than or equal to two, the N clock domain interfaces comprising a one-to-one correspondence with the N phase frequency detectors, the N filters, and the N clock reconstructors, the N phase frequency detectors being respectively coupled to N clock sources, at least two clock sources of the N clock sources being different, and i comprising an integer satisfying a condition 1≤i≤N.
9. The method of claim 8 , further comprising:
receiving, by an (N+1) th phase frequency detector, a clock signal from an external clock source;
sending, by the (N+1) th phase frequency detector, (N+1) th phase difference information between the clock signal from the external clock source and the common reference clock signal to a j th filter in the N filters;
receiving, by the j th filter, the (N+1) th phase difference information from the (N+1) th phase frequency detector;
converting, by the j th filter, the (N+1) th phase difference information into (N+1) th frequency difference information;
sending, by the j th filter, the (N+1) th frequency difference information to a j th clock reconstructor in the N clock reconstructors corresponding to the j th filter;
receiving, by the j th clock reconstructor, the (N+1) th frequency difference information from the j th filter;
reconstructing, by the j th clock reconstructor, an (N+1) th network timing clock according to the common reference clock signal and the (N+1) th frequency difference information; and
sending, by the j th clock reconstructor, the (N+1) th network timing clock to a j th clock domain interface in the N clock domain interfaces, the (N+1) th phase frequency detector being coupled to the external clock source using an external synchronization interface, and j comprising an integer satisfying a condition 1≤j≤N.
10. The method of claim 9 , further comprising:
sending, by a k th filter in the N filters, k th frequency difference information of the k th filter to an (N+1) th clock reconstructor;
receiving, by the (N+1) th clock reconstructor, the k th frequency difference information from the k th filter;
reconstructing, by the (N+1) th clock reconstructor, a k th network timing clock according to the k th frequency difference information; and
sending, by the (N+1) th clock reconstructor, the k th network timing clock to the external synchronization interface, the k comprising an integer satisfying a condition 1≤k≤N.
11. The method of claim 8 , wherein sending the i th phase difference information to the i th filter in the N filters corresponding to the i th phase frequency detector comprises:
sending, by the i th phase frequency detector, the i th phase difference information to an input selector;
receiving, by the input selector, the i th phase difference information from the i th phase frequency detector; and
sending, by the input selector based on a correspondence between the i th phase frequency detector and the i th filter, the i th phase difference information to the i th filter.
12. The method of claim 11 , wherein after receiving the i th phase difference information from the i th phase frequency detector, the method further comprises selecting, by the input selector, M pieces of phase difference information of phase difference information received from the N phase frequency detectors when clock sources of the N clock domain interfaces correspond to M types of services, the M pieces of phase difference information comprising a one-to-one correspondence with the M types of services, sending the i th phase difference information to the i th filter comprising sending, based on a correspondence between the N phase frequency detectors and the N filters, corresponding phase difference information to each filter in the N filters, and the M comprising an integer less than N.
13. The method of claim 8 , wherein sending the i th frequency difference information to the i th clock reconstructor in the N clock reconstructors corresponding to the i th filter comprises:
sending, by the i th filter, the i th frequency difference information to an output selector;
receiving, by the output selector, the i th frequency difference information from the i th filter; and
sending, by the output selector, the i th frequency difference information to the i th clock reconstructor based on a correspondence between the i th filter and the i th clock reconstructor.
14. The method of claim 8 , wherein before sending the i th phase difference information between the common reference clock signal and the clock signal, the method further comprises:
generating, by a common reference clock generator, the common reference clock signal; and
sending, by the common reference clock generator, the common reference clock signal to the i th phase frequency detector and the i th clock reconstructor.