Semiconductor package providing protection from electrical noise
A semiconductor package includes a support member having first and second surfaces opposing each other, having first and second through-holes, spaced apart from each other, and having a wiring structure that connects the first and second surfaces to each other; a connection member disposed on the second surface of the support member and having redistribution layers connected to the wiring structure; a semiconductor chip disposed in the first through-hole and having connection pads connected to the redistribution layers; a second passive component disposed in the second through-hole and connected to the redistribution layers; a first encapsulant disposed on the first surface of the support member and encapsulating the first passive component; and a second encapsulant encapsulating the support member, the first encapsulant, and the semiconductor chip.
1. A semiconductor package comprising:
a support member having first and second surfaces opposing each other, having first and second through-holes spaced apart from each other, and having a wiring structure connecting the first and second surfaces to each other;
a first passive component disposed on the first surface of the support member and connected to the wiring structure;
a connection member disposed on the second surface of the support member and having redistribution layers connected to the wiring structure;
a semiconductor chip disposed in the first through-hole and having connection pads connected to the redistribution layers;
a second passive component disposed in the second through-hole and connected to the redistribution layers;
a first encapsulant disposed on the first surface of the support member and encapsulating the first passive component;
a second encapsulant encapsulating the support member, the first encapsulant, and the semiconductor chip; and
a first shielding layer disposed on side surfaces of the support member and the first encapsulant, and an upper surface of the first encapsulant.
2. The semiconductor package of claim 1 , further comprising a second shielding layer disposed on the second encapsulant and connected to the first shielding layer.
3. The semiconductor package of claim 1 , wherein a side surface of the first encapsulant is substantially coplanar with a side wall of the support member.
4. The semiconductor package of claim 1 , wherein a region of the first surface of the support member on which the first passive component is disposed has a level lower than that of other regions of the first surface of the support member.
5. The semiconductor package of claim 1 , wherein the connection member includes a heat dissipation unit disposed in a region corresponding to the semiconductor chip.
6. The semiconductor package of claim 1 , wherein the first passive component has a size less than that of the second passive component.
7. The semiconductor package of claim 1 , wherein at least one of the first and second passive components includes a plurality of passive components having different sizes.
8. The semiconductor package of claim 1 , wherein a mounted height of the semiconductor chip is higher than a thickness of the support member, and
a height of the upper surface of the first encapsulant is higher than the mounted height of the semiconductor chip.
9. The semiconductor package of claim 1 , wherein the first encapsulant is formed of a same resin as the second encapsulant.
10. The semiconductor package of claim 1 , wherein the second through-hole is a plurality of second through-holes, and the plurality of second through-holes surround the first through-hole.
11. The semiconductor package of claim 1 , wherein the first passive component is disposed on a portion of the support member which separates the first and second through-holes from each other.
12. A semiconductor package comprising:
a support member having first and second surfaces opposing each other, having at least one through-hole, and having a wiring structure connecting the first and second surfaces to each other;
a first passive component disposed on the first surface of the support member and connected to the wiring structure;
a connection member disposed on the second surface of the support member and having redistribution layers connected to the wiring structure;
a semiconductor chip disposed in the at least one through-hole and having connection pads connected to the redistribution layers;
a second passive component disposed in the at least one through-hole and connected to the redistribution layers;
a first encapsulant disposed on the first surface of the support member and encapsulating the first passive component;
a second encapsulant encapsulating the support member, the first encapsulant, the semiconductor chip, and the second passive component; and
a shielding layer disposed on side surfaces of the support member and the first encapsulant, and an upper surface of the first encapsulant,
wherein the first encapsulant has a side surface being substantially coplanar with an inner side surface of the at least one through-hole of the support member.
13. The semiconductor package of claim 12 , wherein the first encapsulant is disposed on the first surface of the support member and has a structure corresponding to the support member.