I/O device scheme for gate-all-around transistors

1. A semiconductor structure comprising:

a plurality of stacked and suspended first semiconductor channel material nanosheets located above a semiconductor substrate and present in an I/O device region, wherein each first semiconductor channel material nanosheet has a channel region having a thickness that is less than a thickness of each end region of the first semiconductor channel material nanosheet;

a I/O device functional gate structure wrapping around the channel region of each first semiconductor channel material nanosheet of the plurality of stacked and suspended first semiconductor channel material nanosheets, wherein a lower portion of the I/O device functional gate structure that is located beneath a bottommost first semiconductor channel material nanosheet of the plurality of stacked and suspended first semiconductor channel material nanosheets extends beneath a topmost surface of the semiconductor substrate; and

a source/drain (S/D) structure on each side of the I/O device functional gate structure and physically contacting sidewalls of each first semiconductor channel material nanosheet of the plurality of stacked and suspended first semiconductor channel material nanosheets.

2. The semiconductor structure of claim 1 , wherein each neighboring pair of suspended first semiconductor channel material nanosheets has an inter-nanosheet spacing distance of from 5 nm to 15 nm.

3. The semiconductor structure of claim 1 , further comprising an inner dielectric spacer contacting a sidewall of the I/O device functional gate structure.

4. The semiconductor structure of claim 1 , further comprising an interlevel dielectric (ILD) material layer located above the source/drain structure.

5. The semiconductor structure of claim 1 , further comprising a source/drain contact structure contacting a surface of the source/drain structure, and a gate contact structure contacting a surface of a gate conductor portion of the I/O device functional gate structure.

6. The semiconductor structure of claim 1 , wherein the I/O device functional gate structure comprises an I/O device interfacial portion, an I/O device gate dielectric portion and an I/O device gate conductor portion.

7. The semiconductor structure of claim 1 , further comprising a logic device region located laterally adjacent to the I/O device region, wherein the logic device region comprises;

a plurality of stacked and suspended second semiconductor channel material nanosheets located on the semiconductor substrate, wherein a logic device functional gate structure wraps around a channel region of each second semiconductor channel material nanosheet of the plurality of stacked and suspended second semiconductor channel material nanosheets, and another source/drain (S/D) structure is located on each side of the logic device functional gate structure and physically contacting sidewalls of each second semiconductor channel material nanosheet of the plurality of stacked and suspended second semiconductor channel material nanosheets.

8. The semiconductor structure of claim 7 , wherein each neighboring pair of suspended second semiconductor channel material nanosheets of the plurality of stacked and suspended second semiconductor channel material nanosheets has a second inter-nanosheet spacing distance that is less than a first inter-nanosheet spacing distance of each neighboring pair of suspended first semiconductor channel material nanosheets.

9. The semiconductor structure of claim 8 , wherein the first inter-nanosheet spacing distance is from 5 nm to 15 nm and the second inter-nanosheet spacing distance is from 12 nm to 25 nm.

10. The semiconductor structure of claim 7 , further comprising a source/drain contact structure contacting a surface of the another source/drain structure, and a gate contact structure contacting a surface of a gate conductor portion of the logic device functional gate structure.

11. The semiconductor structure of claim 7 , wherein the logic device functional gate structure comprises a logic interfacial portion, a logic device gate dielectric portion and a logic device gate conductor portion.

12. A semiconductor structure comprising:

a plurality of stacked and suspended first semiconductor channel material nanosheets located above a semiconductor substrate and present in an I/O device region, wherein each first semiconductor channel material nanosheet has a channel region having a thickness that is less than a thickness of each end region of the first semiconductor channel material nanosheet;

a I/O device functional gate structure wrapping around the channel region of each first semiconductor channel material nanosheet of the plurality of stacked and suspended first semiconductor channel material nanosheets, wherein the I/O device functional gate structure comprises an interfacial oxide portion that is located on an entirety of a topmost surface and a bottommost surface of the channel region of each first semiconductor channel material nanosheet of the plurality of stacked and suspended first semiconductor channel material nanosheets, and wherein a lower portion of the I/O device functional gate structure that is located beneath a bottommost first semiconductor channel material nanosheet of the plurality of stacked and suspended first semiconductor channel material nanosheets extends beneath a topmost surface of the semiconductor substrate; and

a source/drain (S/D) structure on each side of the I/O device functional gate structure and physically contacting sidewalls of each first semiconductor channel material nanosheet of the plurality of stacked and suspended first semiconductor channel material nanosheets.