Semiconductor package and method of manufacturing the same
The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.
1. A substrate, comprising:
a first dielectric layer, having a first surface and a second surface opposite to the first surface;
a first conductive via extending between the first surface and the second surface, the first conductive via comprising:
a bottom pattern at the first surface; and
a top pattern at the second surface;
a first patterned conductive layer on the first surface; and
a second patterned conductive layer on the second surface;
wherein the bottom pattern comprises at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius; and
wherein a shortest distance between any of the at least two geometric centers is greater than 1.4 times of the geometric radius,
wherein an angle formed between a connection line along the shortest distance between any of the at least two geometric centers and the geometric radius is less than 45 degrees, and
wherein the bottom pattern is smaller than the top pattern.
2. The substrate of claim 1 , wherein the first conductive via comprises a tapered shape.
3. The substrate of claim 1 , wherein the at least two geometric patterns comprise four substantially circular shapes, and the at least two geometric centers correspond to four centers of curvatures of the four substantially circular shapes.
4. The substrate of claim 1 , wherein the at least two geometric patterns comprise a plurality of substantially circular shapes arranged in an m by n matrix, wherein m and n are equal to or greater than 2.
5. The substrate of claim 1 , further comprising a second dielectric layer on the second surface of the first dielectric layer, the second dielectric layer further comprising a second conductive via aligning with the first conductive via.
6. The substrate of claim 5 , wherein the second dielectric layer further comprises a third conductive via adjacent to the second conductive via, the third conductive via being narrower than the second conductive via.
7. The substrate of claim 1 , wherein the geometric radius is smaller than about 45 μm.
8. A semiconductor package structure, comprising:
the substrate of claim 1 ;
a semiconductor die over the first surface of the first dielectric layer and electrically coupled to the first patterned conductive layer; and
an encapsulant covering the substrate of claim 1 and the semiconductor die.
9. The semiconductor package structure of claim 8 , further comprising a passive device on the first surface of the first dielectric layer.
10. The semiconductor package structure of claim 8 , wherein the at least two geometric patterns comprise four substantially circular shapes, and the at least two geometric centers correspond to four centers of curvatures of the four substantially circular shapes.
11. The semiconductor package structure of claim 10 , wherein the four substantially circular shapes are under a projection of the semiconductor die.
12. The semiconductor package structure of claim 8 , wherein the at least two geometric patterns comprise a plurality of substantially circular shapes arranged in an m by n matrix, wherein m and n are equal to or greater than 2.
13. The semiconductor package structure of claim 12 , wherein the plurality of substantially circular shapes are not directly under a vertical projection of the semiconductor die.
14. The semiconductor package structure of claim 8 , wherein the first dielectric layer comprises glass cloth.
15. The semiconductor package structure of claim 8 , wherein the semiconductor die is a first semiconductor die, and further comprising a second semiconductor die disposed on the first semiconductor die.
16. The semiconductor package structure of claim 15 , further comprising an adhesive disposed between the first semiconductor die and the second semiconductor die.
17. The semiconductor package structure of claim 16 , wherein the first semiconductor die includes a conductive pad and a conductive bump electrically coupled to the first patterned conductive layer.
18. The semiconductor package structure of claim 17 , wherein the second semiconductor die includes a conductive pad and a conductive bump electrically coupled to the first patterned conductive layer, and wherein the first semiconductor die and the second semiconductor die are disposed back-to-back.
19. The semiconductor package structure of claim 18 , wherein the first semiconductor die is a first type of die, and the second semiconductor die is a second type of die different from the first type.
20. The substrate of claim 1 , wherein the at least two geometric patterns comprise elliptical shape.
21. The substrate of claim 1 , wherein a cross section of the first conductive via comprises a tapered shape.
22. The substrate of claim 1 , wherein the first conductive via comprises five geometric patterns.