IP Library Granted Patent US 12,198,064
Granted Patent B2
US 12,198,064 · App. 16/109,646 · Granted Jan 14, 2025

Systems and methods for determining circuit-level effects on classifier accuracy

Inventors: Kurt F. Busch (Laguna Hills, CA); Jeremiah H. Holleman, III (Irvine, CA); Pieter Vorenkamp (Laguna Beach, CA); Stephen W. Bailey (Irvine, CA)
Assignee: SYNTIANT
G06N3/10G06N3/04G06N3/065G06N3/08G06N3/105
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Quick Facts
Patent No.
US 12,198,064
App. No.
16/109,646
Granted
Jan 14, 2025
Kind
B2
Abstract

A computerized method comprising receiving, by a simulator logic, inputs including: (i) at least one circuit-level characteristic, and (ii) an architectural description of a neural network, modeling, by the simulator logic, execution of the neural network described in the inputs to obtain results representative of what an analog implementation of the neural network would produce, and determining, by the simulator logic, an accuracy of computational analog elements within the analog implementation of the neural network based on the results obtained during modeling of the neural network is described. In some embodiments, the circuit-level characteristic includes thermal or flicker noise, an inaccuracy of weights between nodes within the neural network, or a frequency response variations of an integrated circuit. Additionally, the circuit-level characteristic can be obtained through simulation of an integrated circuit based on technology-specific measurements of the integrated circuit.

Claims (51)

1. A computerized method comprising:

receiving a plurality of inputs by a simulator logic, the inputs including

(i) one or more non-ideal circuit-level characteristics based on technology-specific measurements taken at a foundry, and

(ii) an architectural description of a neural network;

the one or more non-ideal circuit-level characteristics comprising non-linearity of an integrated circuit on which the neural network is processed;

simulating, in one or more software-based simulations performed by the simulator logic, execution of the neural network described in the inputs to obtain results of the one or more simulations, the results being representative of that of an analog implementation of the neural network would produce, wherein the simulating includes modifying a function of the neural network for purposes of simulation to account for a first non-ideal circuit-level characteristic;

in response to a determination that a function is not represented in a framework library associated with the neural network, developing a software module to represent the function;

writing a new extension to the neural network framework library;

writing one or more additional extensions to the neural network framework library based on existing functions including the newly written extension, and comprising one or more modifications that account for an error source or one of the one or more non-ideal circuit-level characteristics;

determining an effect of the one or more non-ideal circuit-level characteristics on a performance of the neural network based on the results of the one or more simulations; and

determining through the one or more simulations a classification accuracy of the neural network.

2. The computerized method of claim 1 , further comprising: determining with the simulator logic an accuracy of analog computational elements within the analog implementation of the neural network based on the results of the one or more simulations obtained during the one or more simulations of the neural network.

3. The computerized method of claim 1 , wherein the results of the one or more simulations obtained during the one or more simulations of the neural network are used to determine specifications required of one or more analog circuits.

4. The computerized method of claim 1 , wherein the one or more non-ideal circuit-level characteristics include at least thermal noise or flicker noise.

5. The computerized method of claim 1 , wherein the one or more non-ideal circuit-level characteristics include at least an inaccuracy of weights between nodes within the neural network.

6. The computerized method of claim 1 , wherein the one or more non-ideal circuit-level characteristics include at least a frequency response variation of a simulated integrated circuit.

7. The computerized method of claim 1 , wherein the architectural description of the neural network includes an output of a neural network development platform selected from TensorFlow, DistBelief, Keras, MXNet, Torch, and Caffe.

8. A method comprising:

receiving a plurality of inputs by a simulator logic, the inputs including;

(i) one or more non-ideal circuit-level characteristics based on technology-specific measurements taken at a foundry, and

(ii) an architectural description of a neural network;

the one or more non-ideal circuit-level characteristics comprising non-linearity of an integrated circuit on which the neural network is processed;

simulating, in one or more software-based simulations performed by the simulator logic, execution of the neural network described in the inputs to obtain results of the one or more simulations, the results being representative of that of an analog implementation of the neural network would produce, wherein the simulating including modifying a function of the neural network for purposes of simulation to account for a first non-ideal circuit-level characteristic;

in response to a determination that a function is not represented in a framework library associated with the neural network, developing a software module to represent the function;

determining an effect of the one or more non-ideal circuit-level characteristics on a performance of the neural network based on the results of the one or more simulations;

determining through the one or more simulations a classification accuracy of the neural network;

writing a new extension to the neural network framework library;

writing one or more additional extensions to the neural network framework library based on an existing function and comprising one or more modifications that account for an error source or one of the one or more non-ideal circuit-level characteristics; and

manufacturing a neuromorphic integrated circuit including the analog implementation of the neural network.

9. The method of claim 8 , further comprising:

developing and providing through a remote service one or more firmware updates for the neuromorphic integrated circuit in accordance with one or more additional simulations.

10. The method of claim 8 , wherein the one or more non-ideal circuit-level characteristics are selected from thermal noise, flicker noise, an inaccuracy of weights between nodes within the neural network, and frequency response variations of a simulated integrated circuit.

11. The method of claim 10 , wherein the one or more non-ideal circuit-level characteristics include thermal noise or flicker noise.

12. The method of claim 10 , wherein the one or more non-ideal circuit-level characteristics include an inaccuracy of weights between nodes within the neural network.

13. The method of claim 10 , wherein the non-ideal one or more circuit-level characteristics include frequency response variations of the simulated integrated circuit.

14. A method comprising:

receiving a plurality of inputs by a simulator logic, the inputs including

(i) one or more non-ideal circuit-level characteristics based on technology-specific measurements taken at a foundry, and

(ii) an architectural description of a neural network;

the one or more non-ideal circuit-level characteristics comprising non-linearity of an integrated circuit on which the neural network is processed, and at least one of thermal noise, flicker noise, an inaccuracy of weights between nodes within the neural network, and frequency response variations of a simulated integrated circuit;

simulating, in one or more software-based simulations performed by the simulator logic, execution of the neural network described in the inputs to obtain results of the one or more simulations, the results being representative of that of an analog implementation of the neural network would produce, wherein the simulating includes modifying a function of the neural network for purposes of simulation to account for a first non-ideal circuit-level characteristic;

in response to a determination that a function is not represented in a framework library associated with the neural network, developing a software module to represent the function;

writing a new extension to the neural network framework library;

writing one or more additional extensions to the neural network framework library based on one or more existing functions and comprising one or more modifications that take into account an error or one of the one or more non-ideal circuit-level characteristics;

determining an effect of the one or more non-ideal circuit-level characteristics on a performance of the neural network as well as classification accuracy of the neural network based on the results of the one or more simulations; and

manufacturing a hardware-based neuromorphic integrated circuit including the analog implementation of the neural network.

15. The method of claim 14 , wherein the one or more non-ideal circuit-level characteristics are obtained through the one or more simulations of the simulated integrated circuit based on technology-specific measurements of the simulated integrated circuit.

16. The method of claim 14 , wherein the neuromorphic integrated circuit includes a number of two-quadrant multipliers in an analog multiplier array configured for filtering or communications decoding, wherein each of the two-quadrant multipliers is configured for two-quadrant multiplication of a signed weight and a non-negative input current value.

17. The method of claim 16 , further comprising:

developing and providing through a remote service one or more firmware updates for the neuromorphic integrated circuit in accordance with one or more additional simulations.

18. The method of claim 14 , wherein the architectural description of the neural network includes an output of a neural network development platform selected from TensorFlow, DistBelief, Kerns, MXNet, Torch, and Caffe.

Assignments (3)
SECURITY INTEREST Recorded Dec 27, 2024
From: SYNTIANT CORP.; PILOT AI LABS, INC.; SYNTIANT TAIWAN LLC; SYNTIANT HOLDINGS LLC
To: OCEAN II PLO LLC
Reel/Frame 069687/0757 →
CORRECTIVE ASSIGNMENT TO CORRECT THE SPELLING OF THE SECOND ASSIGNOR'S NAME PREVIOUSLY RECORDED ON REEL 048373 FRAME 0886. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Feb 21, 2019
From: BUSCH, KURT F.; HOLLEMAN, JEREMIAH H., III; VORENKAMP, PIETER; BAILEY, STEPHEN W.
To: SYNTIANT
Reel/Frame 048395/0896 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 19, 2019
From: BUSCH, KURT F.; HOLLMAN, JEREMIAH H., III; VORENKAMP, PIETER; BAILEY, STEPHEN W.
To: SYNTIANT
Reel/Frame 048373/0886 →
Continuity (2)
Provisional Application 62548892 · Aug 22, 2017
Related Publication 20190065962A1 · Feb 28, 2019
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