Area efficient neuromorphic circuits using field effect transistors (FET) and variable resistance material

1. A neuromorphic circuit comprising:

a first field effect transistor in a first diode configuration establishing an electrical connection between a first gate and a first drain of the first field effect transistor;

a second field effect transistor in a second diode configuration establishing an electrical connection between a second gate and a second drain of the second field effect transistor;

variable resistance material electrically connected to both the first drain and the second drain, the variable resistance material providing a programmable resistance value;

a first junction electrically connected to the variable resistance material and providing a first connection point to an output of a neuron circuit; and

a second junction electrically connected to the variable resistance material and providing a second connection point to the output of the neuron circuit.

2. The neuromorphic circuit of claim 1 further comprising:

a third junction electrically connected to a first source of the first field effect transistor, the third junction providing a connection point to an input of a second neuron circuit; and

a fourth junction electrically connected to a second source of the second field effect transistor, the fourth junction providing a connection point to an input of a third neuron circuit.

3. The neuromorphic circuit of claim 2 wherein the first field effect transistor, the first junction, the third junction, and a portion of the variable resistance material are sized to fit within a first area of six features by six features; and

the second field effect transistor, the second junction, the fourth junction, and a remaining portion of the variable resistance material are sized to fit within a second area of six features by six features that is adjacent to the first area, and further wherein the features are sized according to a manufacturing process used to implement the neuromorphic circuit.

4. The neuromorphic circuit of claim 1 wherein the first gate is electrically coupled to the first junction, providing a current path from the first junction to the first gate that bypasses the variable resistance material.

5. The neuromorphic circuit of claim 1 wherein the first gate is electrically coupled to the variable resistance material, providing a current path from the first junction to the first gate that passes through the variable resistance material.

6. The neuromorphic circuit of claim 1 wherein the neuromorphic circuit is combined with additional neuromorphic circuits to form a synapse block with external interfaces configured to evenly distribute connections to the synapse block.

7. The neuromorphic circuit of claim 1 wherein the variable resistance material is an island of material with separate programmable resistance values with respect to current passing through the first and second field effect transistors, and the variable resistance material is selected from one of: phase change material, metal-oxide, magnetic tunnel junctions, and organic thin film.

8. A method for implementing an area efficient neuromorphic circuit, comprising:

connecting a first field effect transistor in a first diode configuration;

connecting a second field effect transistor in a second diode configuration;

electrically connecting the first field effect transistor and the second field effect transistor to variable resistance material, the variable resistance material providing a programmable resistance value;

connecting a first junction to the variable resistance material to provide a first connection point to an output of a neuron circuit; and

connecting a second junction to the variable resistance material to provide a second connection point to the output of the neuron circuit;

thereby forming a neuromorphic circuit.

9. The method of claim 8 further comprising:

electrically connecting a third junction to the first field effect transistor, the third junction providing a connection point to an input of a second neuron circuit, wherein the first field effect transistor, the first junction, the third junction, and a portion of the variable resistance material are sized to fit within a first area of six features by six features; and

electrically connecting a fourth junction to the second field effect transistor, the fourth junction providing a connection point to an input of a third neuron circuit, wherein the second field effect transistor, the second junction, the fourth junction, and a remaining portion of the variable resistance material are sized to fit within a second area of six features by six features that is adjacent to the first area, and further wherein the features are sized according to a manufacturing process used to implement the neuromorphic circuit.

10. The method of claim 8 further comprising:

providing a current path from the first junction to a first gate of the first field effect transistor that bypasses the variable resistance material.

11. The method of claim 8 further comprising:

providing a current path from the first junction to a first gate of the first field effect transistor that passes through the variable resistance material.

12. The method of claim 8 further comprising:

combining the neuromorphic circuit with additional neuromorphic circuits to form a synapse block; and

offsetting one or more connections to the neuromorphic circuits to evenly distribute the one or more connections to external interfaces of the synapse block.