Implementing scalable memory allocation using identifiers that return a succinct pointer representation

1. A method for memory allocation comprising:

in response to a memory allocation request from a memory allocation requestor, generating, by memory allocation logic, a slab identifier and a hash function identifier indicating a hash function, wherein the slab identifier indicates a memory region associated with a base data size; and

providing, to the memory allocation requestor, a bit string comprising the slab identifier and the hash function identifier.

2. The method of claim 1 , wherein the generating the slab identifier and the hash function identifier comprises generating a concatenated tuple comprising the slab identifier and the hash function identifier.

3. The method of claim 1 , wherein the memory allocation request comprises the base data size and a request identifier, wherein the generating the slab identifier and the hash function identifier comprises:

generating the hash function identifier based on the request identifier corresponding to the memory allocation request; and

generating the slab identifier based on the base data size.

4. The method of claim 3 , wherein:

the request identifier comprises a virtual memory address; and

the generating the hash function identifier is based on the virtual memory address.

5. The method of claim 3 , further comprising:

based on comparing slab metadata corresponding to a plurality of slabs with the base data size, determining a subset of the plurality of slabs corresponding to the base data size, wherein each of the plurality of slabs indicates a distinct memory region; and

selecting, from the subset of the plurality of slabs, a memory location to store data corresponding to the memory allocation request, wherein the generating the slab identifier and the hash function identifier is based on the memory location.

6. The method of claim 5 , further comprising:

determining, based on the request identifier and a plurality of hash functions, a plurality of candidate slots from the subset of the plurality of slabs, wherein the selecting the memory location is based on the plurality of candidate slots.

7. The method of claim 6 , further comprising:

determining, based on the plurality of candidate slots, a viable candidate slot indicating the memory location; and

storing the data in the memory location.

8. The method of claim 7 , further comprising:

determining a bit vector corresponding to the plurality of candidate slots within the subset of the plurality of slabs; and

determining, based on performing an operation on the bit vector, the viable candidate slot.

9. The method of claim 8 , wherein performing the operation on the bit vector comprises performing an atomic operation on the bit vector.

10. The method of claim 8 , wherein performing the operation on the bit vector comprises performing a read operation on the bit vector, a set operation on the bit vector, and an update operation on the bit vector.

11. The method of claim 8 , further comprising:

performing an atomic update operation to update the bit vector based on storing the data in the memory location.

12. The method of claim 11 , wherein performing the atomic update operation to update the bit vector comprises performing an atomic OR operation.

13. The method of claim 11 , wherein performing the atomic update operation to update the bit vector comprises performing an atomic Compare-and-Exchange operation.

14. The method of claim 1 , further comprising:

retrieving data corresponding to the memory allocation request based on the slab identifier and the hash function identifier.

15. A processor comprising:

memory allocation logic configured to:

in response to a memory allocation request from a memory allocation requestor, generate a slab identifier and a hash function identifier indicating a hash function, wherein the slab identifier indicates a memory region associated with a base data size; and

provide, to the memory allocation requestor, a bit string comprising the slab identifier and the hash function identifier.

16. The processor of claim 15 , wherein the memory allocation logic generates the slab identifier and the hash function identifier by:

generating a concatenated tuple comprising the slab identifier and the hash function identifier.

17. The processor of claim 15 , wherein the memory allocation request comprises the base data size and a request identifier, and wherein the memory allocation logic generates the slab identifier and the hash function identifier by:

generating the hash function identifier based on the request identifier corresponding to the memory allocation request; and

generating the slab identifier based on the base data size.

18. The processor of claim 17 , wherein:

the request identifier comprises a virtual memory address; and

the memory allocation logic generates the hash function identifier based on the virtual memory address.

19. The processor of claim 17 , wherein:

the request identifier comprises a physical memory address; and

the memory allocation logic generates the hash function identifier based on the physical memory address.

20. The processor of claim 17 , wherein the memory allocation logic is further configured to:

based on comparing slab metadata corresponding to a plurality of slabs with the base data size, determine a subset of the plurality of slabs corresponding to the base data size, wherein each of the plurality of slabs indicates a distinct memory region; and

select, from the subset of the plurality of slabs, a memory location to store data corresponding to the memory allocation request, wherein the generating the slab identifier and the hash function identifier is based on the memory location.

21. The processor of claim 20 , wherein the memory allocation logic is further configured to:

determine, based on the request identifier and a plurality of hash functions, a plurality of candidate slots from the subset of the plurality of slabs, wherein the selecting the memory location is based on the plurality of candidate slots.

22. The processor of claim 21 , wherein the memory allocation logic is further configured to:

determine, based on the plurality of candidate slots, a viable candidate slot indicating the memory location; and

store the data in the memory location.

23. The processor of claim 22 , wherein the memory allocation logic is further configured to:

determine a bit vector corresponding to the plurality of candidate slots within the subset of the plurality of slabs; and

determine, based on performing an operation on the bit vector, the viable candidate slot.

24. The processor of claim 23 , wherein the memory allocation logic performs the operation on the bit vector by performing an atomic operation on the bit vector.

25. The processor of claim 23 , wherein the memory allocation logic performs the operation on the bit vector by performing a read operation on the bit vector, a set operation on the bit vector, and an update operation on the bit vector.

26. The processor of claim 23 , wherein the memory allocation logic is further configured to:

perform an atomic update operation to update the bit vector based on storing the data in the memory location.

27. The processor of claim 26 , wherein the memory allocation logic performs the atomic update operation to update the bit vector by performing an atomic OR operation.

28. The processor of claim 26 , wherein the memory allocation logic performs the atomic update operation to update the bit vector by performing an atomic Compare-and-Exchange operation.

29. The processor of claim 15 , wherein the memory allocation logic is further configured to:

retrieve data corresponding to the memory allocation request based on the slab identifier and the hash function identifier.

30. A processor comprising:

memory allocation logic configured to:

obtain, from a memory allocation requestor, a memory allocation request comprising a request identifier and a base data size;

determine, based on comparing slab metadata corresponding to a plurality of slabs with the base data size, a subset of the plurality of slabs associated with the base data size, wherein each of the plurality of slabs indicates a distinct memory region;

determine, based on the request identifier and a plurality of hash functions, a plurality of candidate slots from the subset of the plurality of slabs;

select, from the plurality of candidate slots, a memory location to store data corresponding to the memory allocation request;

generate, based on the memory location, a slab identifier and a hash function identifier; and

provide, to the memory allocation requestor, a bit string comprising the slab identifier and the hash function identifier.

31. The processor of claim 30 , wherein the memory allocation logic generates the slab identifier and the hash function identifier by:

generating a concatenated tuple comprising the slab identifier and the hash function identifier.

32. The processor of claim 30 , wherein the memory allocation logic is further configured to:

determine a bit vector corresponding to the plurality of candidate slots within the subset of the plurality of slabs; and

determine, based on performing an operation on the bit vector, the memory location.

33. The processor of claim 32 , wherein the memory allocation logic performs the operation on the bit vector by performing an atomic operation on the bit vector.

34. The processor of claim 32 , wherein the memory allocation logic performs the operation on the bit vector by performing a read operation on the bit vector, a set operation on the bit vector, and an update operation on the bit vector.

35. The processor of claim 32 , wherein the memory allocation logic is further configured to:

perform an atomic update operation to update the bit vector based on the memory location.

36. The processor of claim 35 , wherein the memory allocation logic performs the atomic update operation to update the bit vector by performing an atomic OR operation.

37. The processor of claim 35 , wherein the memory allocation logic performs the atomic update operation to update the bit vector by performing an atomic Compare-and-Exchange operation.