IP Library Granted Patent US 10,802,997
Granted Patent B2
US 10,802,997 · App. 16/111,668 · Granted Oct 13, 2020

Method for controlling power supply voltage in semiconductor integrated circuit

Inventors: Hironori Kubo (Osaka, JP); Norihiko Mizobata (Osaka, JP); Makoto Hirano (Osaka, JP); Akihiro Suzuki (Osaka, JP); Masahiro Takeuchi (Osaka, JP)
Assignee: SOCIONEXT INC.
G06F13/1689G05F1/12G11C5/147G06F1/3243G06F1/3296
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Quick Facts
Patent No.
US 10,802,997
App. No.
16/111,668
Granted
Oct 13, 2020
Kind
B2
Abstract

A semiconductor integrated circuit operates with a voltage supplied from a first power supply IC to transmit and receive data to and from an external memory. The semiconductor integrated circuit includes: an interface circuit operating with a voltage supplied from a second power supply IC and accessing the external memory to transmit and receive data to and from the external memory; a determination circuit which determines, based on a result of the access by the interface circuit, an AC timing specification between the external memory and the interface circuit to generate control information for controlling an output voltage of the second power supply IC in accordance with the AC timing specification; and a voltage control circuit which controls the output voltage of the second power supply IC in accordance with the control information.

Claims (11)

1. A method in a semiconductor integrated circuit including an interface circuit, a part of the semiconductor integrated circuit other than the interface circuit being supplied a voltage from a first power supply integrated circuit (IC) dynamically changing an output voltage of the first power supply IC, for controlling a voltage supplied from a second power supply IC different from the first power supply IC to the interface circuit, the method comprising steps of:

(a) accessing an external memory to transmit and receive data to and from the external memory, by the interface circuit;

(b) changing a control information for controlling an output voltage of the second power supply IC independently from the first power supply IC based on a result of the access done by the interface circuit; and

(c) transmitting or receiving data to or from the external memory by the interface circuit with the controlled output voltage of the second power supply IC.

2. The method of claim 1 , wherein the step (b) includes determining an alternate current (AC) timing specification between the external memory and the interface circuit.

3. The method of claim 2 , wherein the step (b) includes changing the control information to indicate the output voltage of the second power supply IC be lowered if the AC timing specification is larger than a predetermined value, and the output voltage of the second power supply IC be raised if the AC timing specification is smaller than the predetermined value.

4. The method of claim 2 , the in the step (b), the control information is changed further based on a stored value of the voltage to be output by the second power supply IC, wherein the AC timing specification is associated with the value.

5. The method of claim 1 , wherein the step (a) is done in a test mode and the step (c) is done in a normal mode.

6. The method of claim 1 , wherein in the step (b), the control information is changed further based on temperature information from a temperature sensor within the semiconductor integrated circuit.

7. The method of claim 1 , wherein in the step (b), the control information is changed further based on the interface circuit's own process induced variation from a process sensor within the semiconductor integrated circuit.

8. The method of claim 1 , wherein in the step (b), the control information is changed further based on a voltage from a voltage monitor within the semiconductor integrated circuit.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE INVENTORS PREVIOUSLY RECORDED ON REEL 046696 FRAME 0118. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 17, 2019
From: KUBO, HIRONORI; MIZOBATA, NORIHIKO; HIRANO, MAKOTO; SUZUKI, AKIHIRO; TAKEUCHI, MASAHIRO
To: SOCIONEXT INC.
Reel/Frame 049218/0148 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2018
From: KUBO, HIRONORI; MIZOBATA, NIRIHIKO; HIRANO, MAKOTO; SUZUKI, AKIHIRO
To: SOCIONEXT INC.
Reel/Frame 046696/0118 →
Priority Claims (1)
JP 2013-122327 · Jun 11, 2013 · national
Continuity (3)
Continuation 14964435 · Dec 9, 2015
Continuation PCTJP2014001890 · Mar 31, 2014
Related Publication 20180365178A1 · Dec 20, 2018