Low dropout (LDO) voltage regulator with soft-start circuit

1. A low dropout (LDO) voltage regulator comprising:

a differential amplifier;

a pass transistor coupled to an output of the differential amplifier, the pass transistor configured to provide an output voltage of the LDO voltage regulator; and

a soft-start circuit coupled to the differential amplifier, the soft-start circuit configured to adjust a soft-start driving signal to control a slope of the output voltage based on the output voltage during a start-up operation of the LDO voltage regulator,

the soft-start circuit including:

a plurality of first transistors defining a first voltage threshold;

a plurality of second transistors defining a second voltage threshold;

a clamp transistor connected to the output of the differential amplifier;

a clamp capacitor connected to the clamp transistor; and

a current source selectively connected to the clamp capacitor via a switch.

2. The LDO voltage regulator of claim 1 , wherein a voltage slope on the clamp capacitor is the soft-start driving signal such that the voltage slope changes at least once during the start-up operation of the LDO voltage regulator.

3. The LDO voltage regulator of claim 1 , wherein the start- up operation includes a first phase, a second phase, and a third phase, wherein the clamp capacitor is charged faster in the first phase than the second phase.

4. The LDO voltage regulator of claim 3 , wherein the soft-start driving signal includes a first voltage slope during the first phase, a second voltage slope during the second phase, and a third voltage slope during the third phase, the first voltage slope being different than the second voltage slope, the third voltage slope being different than the second voltage slope.

5. The LDO voltage regulator of claim 1 , wherein the clamp capacitor is connected to a gate of the clamp transistor.

6. The LDO voltage regulator of claim 1 , wherein the differential amplifier includes an N-channel metal oxide-semiconductor (NMOS) amplifier, and the pass transistor includes a P-channel transistor.

7. The LDO voltage regulator of claim 1 , wherein the differential amplifier includes a P-channel metal oxide-semiconductor (PMOS) amplifier, and the pass transistor includes an N-channel transistor.

8. The LDO voltage regulator of claim 1 , wherein the current source of the soft-start circuit is a first current source, and the soft-start circuit includes a second current source connected to the clamp capacitor, further comprising:

a driver coupled to the differential amplifier and the pass transistor.

9. The LDO voltage regulator of claim 1 , wherein the soft-start circuit is configured to adjust the slope in response to the output voltage exceeding the first voltage threshold and adjust the slope in response to the output voltage exceeding the second voltage threshold.

10. A low dropout (LDO) voltage regulator comprising:

a differential amplifier;

a pass transistor coupled to an output of the differential amplifier, the pass transistor configured to provide an output voltage of the LDO voltage regulator; and

a soft-start circuit coupled to the differential amplifier, the soft-start circuit including:

a plurality of first transistors defining a first voltage threshold;

a plurality of second transistors defining a second voltage threshold;

a clamp transistor connected to the output of the differential amplifier; and

a clamp capacitor connected to the clamp transistor, the clamp capacitor configured to be charged during a start-up operation of the LDO voltage regulator to control an increase of the output voltage,

the soft-start circuit configured to cause the clamp capacitor to have a first voltage slope in a first phase of the start-up operation and a second voltage slope in a second phase of the start-up operation, the second voltage slope being different than the first voltage slope, at least one of the first phase or the second phase having a duration that is determined based on a value of the output voltage.

11. The LDO voltage regulator of claim 10 , wherein the soft-start circuit is configured to determine a start of the first phase in response to an enable signal, and the soft-start circuit is configured to determine a start of the second phase in response to the output voltage exceeding the first voltage threshold.

12. The LDO voltage regulator of claim 11 , wherein the soft-start circuit is configured to cause the clamp capacitor to have a third voltage slope in a third phase of the start-up operation, the third voltage slope being different than the second voltage slope.

13. The LDO voltage regulator of claim 12 , wherein the soft-start circuit is configured to determine a start of the third phase in response to the output voltage exceeding the second voltage threshold.

14. The LDO voltage regulator of claim 10 , wherein the soft-start circuit includes a first current source and a second current source, the first current source being connected to the clamp capacitor, the second current source being connected to the clamp capacitor via a transistor.

15. The LDO voltage regulator of claim 10 ,

wherein the soft-start circuit is configured to determine a start of the first phase in response to an enable signal, determine a start of the second phase in response to the output voltage exceeding the first voltage threshold, and determine a start of a third phase in response to the output voltage exceeding the second voltage threshold.

16. The LDO voltage regulator of claim 10 , wherein the output voltage reaches a nominal value after the start-up operation, the nominal value being equal to or greater than the reference voltage.

17. The LDO voltage regulator of claim 10 , further comprising:

a driver coupled to the differential amplifier and the pass transistor.

18. A method for operating a low dropout (LDO) voltage regulator, the method comprising:

charging a soft-start circuit during a start-up operation of the LDO voltage regulator, the soft-start circuit including a clamp transistor connected to an output of a differential amplifier, and a clamp capacitor connected to the clamp transistor, the charging including:

generating, in response to an enable signal, a first voltage slope on the clamp capacitor during a first phase of the start-up operation;

generating, in response to the output voltage exceeding a first voltage threshold defined by a plurality of first transistors, a second voltage slope on the clamp capacitor during a second phase of the start-up operation, the second voltage slope being different than the first voltage slope;

generating, in response to the output voltage exceeding a second voltage threshold defined by a plurality of second transistors, a third voltage slope on the clamp capacitor during a third phase of the start-up operation, the third voltage slop being different than the second voltage slope; and

increasing an output voltage of the LDO voltage regulator based on the first voltage slope, the second voltage slope, and the third voltage slope.