IP Library Granted Patent US 10,916,508
Granted Patent B2
US 10,916,508 · App. 16/114,053 · Granted Feb 9, 2021

Semiconductor device package with radiation shield

Inventor: Yasuo Takemoto (Kamakura Kanagawa, JP)
Assignee: TOSHIBA MEMORY CORPORATION
H01L23/556H01L21/563H01L23/295H01L23/5389H01L24/11H01L24/14H01L24/27H01L24/32H01L24/48H01L24/83H01L25/18H01L25/50H01L2224/13099H01L2224/325H01L2224/48599H01L2924/01028H01L2924/01029H01L2924/1434
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Quick Facts
Patent No.
US 10,916,508
App. No.
16/114,053
Granted
Feb 9, 2021
Kind
B2
Abstract

A semiconductor device includes a substrate and a semiconductor chip. The semiconductor chip includes a semiconductor element on a first surface thereof. The semiconductor chip is provided on the substrate such that a second surface thereof, which is opposite to the first surface, faces an upper surface of the substrate. A metal layer is provided between the second surface of the semiconductor chip and the upper surface of the substrate. A metal material, in which the range of α rays is shorter than for single-crystal silicon, is used in the metal layer.

Claims (27)

1. A semiconductor device comprising:

a substrate;

a semiconductor chip including a semiconductor element on a first surface of the semiconductor chip, the semiconductor chip provided on the substrate such that a second surface of the semiconductor chip, opposite to the first surface, faces an upper surface of the substrate;

a metal layer provided between the second surface of the semiconductor chip and the upper surface of the substrate; and

a resin layer provided on the first surface of the semiconductor chip and the upper surface of the substrate, the resin layer covering the metal layer for preventing exposure to outside air,

wherein the metal layer includes a metal material in which a range of a rays is shorter than for single-crystal silicon, and

wherein the resin layer is directly in contact with the upper surface of the substrate.

2. The semiconductor device according to claim 1 , wherein the semiconductor chip comprises at least one of a memory controller or a memory region.

3. The semiconductor device according to claim 1 , wherein the semiconductor chip comprises a memory controller and a memory region.

4. The semiconductor device according to claim 1 , further comprising a plurality of memory chips, and

wherein the semiconductor chip comprises a memory controller.

5. The semiconductor device according to claim 1 , further comprising an adhesive layer disposed between the metal layer and the substrate.

6. The semiconductor device according to claim 1 , wherein the metal layer covers an entirety of the second surface of the semiconductor chip.

7. The semiconductor device according to claim 1 , wherein, given that a density of a certain material is “p”, a range of α-rays in air is “R”, and an atomic weight of the material is “A”, a range of α-rays in the material, “Rs”, is defined by Equation 1 as follows:

Rs =(3.2×10 −4 ×R×A 1/2 )/ρ  (Equation 1),

wherein an Rs of the metal layer is smaller than an Rs of single-crystal silicon.

8. The semiconductor device according to claim 1 , wherein the metal material is copper or nickel.

9. The semiconductor device according to claim 1 , wherein the metal layer has a film thickness of 20 μm or less.

10. The semiconductor device according to claim 1 , wherein the substrate is made of a glass resin material in which a resin contains a glass fiber.

11. The semiconductor device according to claim 1 , further comprising:

a solder resist layer provided on the upper surface of the substrate,

wherein the solder resist layer includes a glass filler.

12. The semiconductor device according to claim 1 , wherein the metal layer is in contact with the second surface of the semiconductor chip.

13. The semiconductor device according to claim 1 , further comprising:

a first adhesive layer provided on the upper surface of the substrate; and

a second adhesive layer provided on the second surface of the semiconductor chip,

wherein the metal layer is provided between the first adhesive layer and the second adhesive layer.

Assignments (4)
CHANGE OF NAME AND ADDRESS Recorded Feb 4, 2022
From: K.K PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 058957/0124 →
CHANGE OF NAME AND ADDRESS Recorded Jan 31, 2022
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 058905/0582 →
MERGER Recorded Jan 31, 2022
From: TOSHIBA MEMORY CORPORATION
To: K.K PANGEA
Reel/Frame 058946/0675 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2018
From: TAKEMOTO, YASUO
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 047400/0246 →
Priority Claims (1)
JP 2018-048194 · Mar 15, 2018 · national
Continuity (1)
Related Publication 20190287922A1 · Sep 19, 2019