IP Library › Granted Patent US 10,565,141
Granted Patent B1
US 10,565,141 · App. 16/114,744 · Granted Feb 18, 2020

Systems and methods for hiding operating system kernel data in system management mode memory to thwart user mode side-channel attacks

Inventors: Craig L. Chaiken (Pflugerville, TX); Michael W. Arms (Pflugerville, TX); Ricardo L. Martinez (Leander, TX)
Assignee: Dell Products L.P.
G06F13/24G06F9/4403G06F13/1673G06F21/74
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Quick Facts
Patent No.
US 10,565,141
App. No.
16/114,744
Granted
Feb 18, 2020
Kind
B1
Abstract

Systems and methods are provided that may be implemented to hide operating system kernel data in system management mode memory. An information handling system includes a system memory, central processing unit (CPU), and Basic Input Output System (BIOS). The CPU is operable in a system management mode and is programmable to specify an SMM region of the system memory that is only accessible when the CPU is operating in the SMM. The BIOS is programmed to save kernel data from a non-SMM region of the system memory to the SMM region and then clear the kernel data from the non-SMM region in response to an operating system (OS) generating a system management interrupt (SMI) and to restore the kernel data to the non-SMM region of the system memory from the SMM region in response to the OS generating a SMI.

Claims (69)

1. An information handling system, comprising:

a system memory;

a central processing unit (CPU) operable in a system management mode (SMM), wherein the CPU is programmable to specify an SMM region of the system memory that is only accessible when the CPU is operating in the SMM; and

a Basic Input Output System (BIOS) programmed to:

save kernel data from a non-SMM region of the system memory to the SMM region and then clear the kernel data from the non-SMM region to hide the kernel data within the SMM region from a user mode code only in response to an operating system (OS) generating a first system management interrupt (SMI) at a kernel privilege level before switching the CPU from a kernel privilege level to a user privilege level; and

then restore the kernel data to the non-SMM region of the system memory from the SMM region only in response to the OS generating a second SMI after switching the CPU from the user privilege level back to the kernel privilege level.

2. The information handling system of claim 1 ,

wherein the non-SMM region comprises a buffer into which the OS previously copies the kernel data from a kernel data area of the system memory, the OS also previously clearing the kernel data from the kernel data area after copying the kernel data into the buffer.

3. The information handling system of claim 2 ,

wherein the BIOS is further programmed to:

report the address of the buffer to the OS via the ACPI table.

4. The information handling system of claim 3 ,

wherein the BIOS is further programmed to:

allocate the buffer of type EfiRuntimeServicesData prior to reporting the address of the buffer to the OS via the ACPI table.

5. The information handling system of claim 1 ,

wherein the BIOS is further programmed to:

refrain from performing the save/restore of the kernel data to/from the SMM region if the SMI was not generated at a kernel privilege level.

6. The information handling system of claim 5 ,

wherein the BIOS is further programmed to:

determine whether the SMI was generated at a kernel privilege level by examining a SMI saved CPU state from the SMM region.

7. The information handling system of claim 1 ,

wherein the BIOS is further programmed to:

set a flag in an Advanced Configuration and Power Interface (ACPI) table of the system to indicate an ability of the BIOS to perform the save/restore of the kernel data to/from the SMM region.

8. The information handling system of claim 1 ,

wherein the BIOS is further programmed to:

insert one or more SMI handlers to perform the save/restore of the kernel data to/from the SMM region ahead of all other SMI handlers in the system.

9. The information handling system of claim 8 ,

wherein the BIOS is further programmed to:

update an Advanced Configuration and Power Interface (ACPI) table of the system to identify the one or more SMI handlers.

10. A non-transitory computer-readable medium (NTCRM) having instructions of an operating system (OS) stored thereon for execution by a CPU to perform operations comprising:

only prior to switching the CPU from a kernel privilege level to a user privilege level:

copying kernel data from a kernel data area of a system memory to a buffer;

clearing the kernel data from the kernel data area; and

invoking a Basic Input Output System (BIOS) to save the kernel data from the buffer to a system management mode (SMM) region of the system memory accessible only when the CPU is operating in SMM and to clear the kernel data from the buffer after saving the kernel data to the SMM region to hide the kernel data within the SMM region from a user mode code; and

only upon resuming from the user privilege level to the kernel privilege level:

invoking the BIOS to restore the kernel data to the buffer from the SMM region; and

copying the kernel data from the buffer to the kernel data area.

11. The NTCRM of claim 10 , having instructions of the operating system (OS) stored thereon for execution by the CPU to perform further operations comprising:

obtaining an address of the buffer from an Advanced Configuration and Power Interface (ACPI) table of the system.

12. The NTCRM of claim 10 , having instructions of the operating system (OS) stored thereon for execution by the CPU to perform further operations comprising:

examine a flag in an Advanced Configuration and Power Interface (ACPI) table of the system to determine whether the BIOS includes the ability to save/restore the kernel data to/from the SMM region; and

refraining from said invoking the BIOS to save/restore the kernel data if the BIOS does not include the ability to save/restore the kernel data.

13. The NTCRM of claim 10 , having instructions of the operating system (OS) stored thereon for execution by the CPU to perform further operations comprising:

invoking an alternate method of saving/restoring the kernel data if the BIOS does not include the ability to save/restore the kernel data.

14. The NTCRM of claim 10 , having instructions of the operating system (OS) stored thereon for execution by the CPU to perform further operations comprising:

clearing the kernel data from the buffer after said copying the kernel data from the buffer to the kernel data area.

15. The NTCRM of claim 10 ,

wherein said invoking the BIOS to save/restore the kernel data comprises generating a system management interrupt (SMI).

16. A method, comprising:

only while operating a central processing unit (CPU) at a kernel privilege level, invoking an interrupt handler that saves data from a first memory location that resides in a first address space associated with a first operating mode of the CPU to a second memory location that resides in a second address space associated with a second operating mode of the CPU and overwrites the data in the first memory location to hide the data within the second address space from a user mode code;

wherein the second address space is accessible only when operating the CPU in the second operating mode;

then switching the CPU from operating at the kernel privilege level to a user privilege level;

then executing code at the user privilege level;

then switching the CPU back from operating at the user privilege level to operating at the kernel privilege level; and

then only after switching the CPU back to operating at the kernel privilege level, invoking an interrupt handler that restores the data from the second memory location to the first memory location.

17. The method of claim 16 , further comprising:

copying, by an operating system (OS) at the kernel privilege level, the data from a kernel data area to the first memory location and overwriting the data in the kernel data area prior to said invoking an interrupt handler that saves data from a first memory location;

copying, by the OS at the kernel privilege level, the data to the kernel data area from the first memory location after said invoking an interrupt handler that restores the data from a first memory location; and

wherein the first memory location is allocated by a Basic Input Output System (BIOS) that provides an address of the first memory location to the OS via an Advanced Configuration and Power Interface (ACPI) table.

18. The method of claim 16 ,

wherein the second operating mode is a system management mode (SMM) of the CPU; and

wherein said interrupt handlers comprise system management interrupt (SMI) handlers.

19. The method of claim 16 ,

refraining, by the interrupt handler, from saving/restoring the data if the interrupt handler is not invoked at the kernel privilege level.

20. The method of claim 16 , further comprising:

setting, by a Basic Input Output System (BIOS) at system boot time, a flag in an Advanced Configuration and Power Interface (ACPI) table to indicate the BIOS supports invocation of the interrupt handlers that save/restore the data; and

determining, by an operating system via the ACPI table flag, whether the BIOS supports invocation of the interrupt handlers that save/restore the data.

21. The method of claim 16 , further comprising overwriting the data in the first memory location to prevent a user mode side-channel attack by hiding the data within the second address space from the user mode code.

22. The information handling system of claim 1 , where the BIOS is programmed to clear the kernel data from the non-SMM region to prevent a user mode side-channel attack by hiding the kernel data within the SMM region from the user mode code.

Assignments (4)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2018
From: CHAIKEN, CRAIG L.; ARMS, MICHAEL W.; MARTINEZ, RICARDO L.
To: DELL PRODUCTS L.P.
Reel/Frame 046726/0535 →
Cited By (1)
US 12,333,004