Semiconductor structures and fabrication methods thereof
A semiconductor structure includes a substrate. The substrate includes a plurality of function regions and a plurality of heat-dissipation regions. Each heat-dissipation region is adjacent to at least one function region. The semiconductor structure also includes a plurality of active fin structures, protruding from the substrate of the plurality of function regions; a plurality of channel layers, each formed on an active fin structure; and a plurality of heat-dissipation fin structures, protruding from the substrate of the plurality of heat-dissipation regions.
1. A semiconductor structure, comprising:
a substrate, including a plurality of function regions and a plurality of heat-dissipation regions, wherein each heat-dissipation region is adjacent to at least one function region;
a plurality of active fin structures, protruding from the substrate of the plurality of function regions;
a plurality of channel layers, each formed on an active fin structure; and
a plurality of heat-dissipation fin structures, protruding from the substrate of the plurality of heat-dissipation regions;
a plurality of trenches formed in each of the plurality of heat-dissipation fin structures.
2. The semiconductor structure according to claim 1 , wherein:
the plurality of heat-dissipation regions are arranged on both sides of the plurality of function regions; or
the plurality of heat-dissipation regions and the plurality of function regions are alternately arranged.
3. The semiconductor structure according to claim 1 , wherein:
the substrate, the plurality of active fin structures, and the plurality of heat-dissipation fin structures together form a single-piece structure.
4. The semiconductor structure according to claim 3 , wherein:
the substrate, the plurality of active fin structures, and the plurality of heat-dissipation fin structures are made of Si.
5. The semiconductor structure according to claim 1 , wherein:
a number of the plurality of heat-dissipation fin structures is smaller than or equal to a number of the plurality of active fin structures.
6. The semiconductor structure according to claim 1 , wherein:
the plurality of heat-dissipation fin structures are arranged parallel to each other; and
a distance between adjacent heat-dissipation fin structures is in a range of approximately 30 nm to 100 nm.
7. The semiconductor structure according to claim 1 , wherein:
in a direction perpendicular to a length direction of the plurality of active fin structures, the plurality of heat-dissipation regions are arranged on at least one side of each function region; and
the plurality of heat-dissipation fin structures are parallel to the plurality of active fin structures.
8. The semiconductor structure according to claim 7 , wherein:
a distance from a heat-dissipation fin structure to an active fin structure adjacent to the heat-dissipation fin structure is in a range of approximately 40 nm to 90 nm.
9. The semiconductor structure according to claim 1 , wherein:
the semiconductor structure is a P-type metal-oxide-semiconductor transistor (PMOS) device; and
the plurality of channel layers are made of SiGe.
10. The semiconductor structure according to claim 1 , wherein:
the semiconductor structure is an N-type metal-oxide-semiconductor transistor (NMOS) device; and
the plurality of channel layers are made of a Group III-V semiconductor material.
11. The semiconductor structure according to claim 10 , wherein:
the plurality of channel layers are made of InGaAs or InAs.
12. A semiconductor structure, comprising:
a substrate, including a plurality of function regions and a plurality of heat-dissipation regions, wherein each heat-dissipation region is adjacent to at least one function region;
a plurality of active fin structures, protruding from the substrate of the plurality of function regions;
a plurality of channel layers, each formed on an active fin structure;
a plurality of heat-dissipation fin structures, protruding from the substrate of the plurality of heat-dissipation regions; and
a plurality of trenches formed in each heat-dissipation fin structure, wherein:
in a direction perpendicular to a length direction of the plurality of active fin structures, the plurality of heat-dissipation regions are arranged on at least one side of each function region,
the plurality of heat-dissipation fin structures are parallel to the plurality of active fin structures, and
the plurality of trenches divide the heat-dissipation fin structure into multiple heat-dissipation sections arranged in a length direction of the heat-dissipation fin structure.
13. The semiconductor structure according to claim 12 , further including:
a plurality of gate structures, formed across the plurality of channel layers and covering a portion of top and sidewall surfaces of the plurality of channel layers, wherein:
the plurality of gate structures extend to the plurality of trenches, and intersect with the plurality of heat-dissipation fin structures at the plurality of trenches.
14. The semiconductor structure according to claim 13 , further including:
an interconnection structure, formed on the plurality of channel layers on each side of the plurality of gate structures, wherein:
the interconnection structure extends to cover a portion of top surfaces of the heat-dissipation sections.
15. A method for fabricating a semiconductor structure, comprising:
providing a substrate, including a plurality of function regions and a plurality of heat-dissipation regions, wherein each heat-dissipation region is adjacent to at least one function region;
forming a plurality of active fin structures protruding from the substrate of the plurality of function regions, and a plurality of heat-dissipation fin structures protruding from the substrate of the plurality of heat-dissipation regions;
forming a plurality of trenches in each of the plurality of heat-dissipation fin structures;
forming a dielectric layer on the substrate, wherein the dielectric layer exposes the plurality of the active fin structures; and
removing a portion of each active fin structure to form a plurality of fin-structure openings in the dielectric layer; and
forming a plurality of channel layers in the plurality of fin-structure openings on top of a remaining portion of the plurality of active fin structures.
16. The method according to claim 15 , wherein forming the plurality of active fin structures and the plurality of heat-dissipation fin structures includes:
forming a fin structure material layer on the substrate;
forming a fin-structure mask layer on the fin-structure material layer, wherein the fin-structure mask layer defines positions and dimensions of the plurality of active fin structures and the plurality of heat-dissipation fin structures; and
forming the plurality of active fin structures protruding from the substrate of the plurality of function regions and the plurality of heat-dissipation fin structures protruding from the substrate of the plurality of heat-dissipation regions by etching the fin-structure material layer using the fin-structure mask layer as an etch mask.
17. The method according to claim 16 , wherein:
forming the plurality of trenches in each heat-dissipation fin structure is after forming the plurality of active fin structures and the plurality of heat-dissipation fin structures and prior to forming the dielectric layer, and
wherein:
the plurality of trenches divide the heat-dissipation fin structure into multiple heat-dissipation sections arranged in a length direction of the heat-dissipation fin structure.
18. The method according to claim 17 , after forming the plurality of channel layers, further including:
removing a portion of the dielectric layer to expose a portion of sidewall surfaces of the plurality of channel layers; and
forming a plurality of gate structures across the plurality of channel layers to cover a portion of top and sidewall surfaces of the plurality of channel layers, wherein:
the plurality of gate structures extend to the plurality of trenches, and intersect with the plurality of heat-dissipation fin structures at the plurality of trenches.
19. The method according to claim 18 , after forming the plurality of gate structures, further including:
forming an interconnection structure on the plurality of channel layers on each side of the plurality of gate structures, wherein:
the interconnection structure extends to cover a portion of top surfaces of the heat-dissipation sections.
20. The method according to claim 15 , wherein:
the plurality of channel layers are formed in the plurality of fin-structure openings through epitaxial growth.