IP Library › Granted Patent US 10,383,228
Granted Patent B2
US 10,383,228 · App. 16/116,156 · Granted Aug 13, 2019

Electronic component device and method for manufacturing the same

Inventor: Masahiro Kyozuka (Nagano, JP)
Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
H05K1/144H01L21/486H01L23/3121H01L23/3135H01L23/5385H01L23/5389H01L25/105H01L25/50H01L23/49811H01L23/5384H01L25/0655H01L2224/16227H01L2224/32225H01L2224/73204H01L2225/1023H01L2225/1041H01L2225/1058H01L2924/1533H01L2924/15311H01L2924/18161H05K2201/042H05K2201/10242
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Quick Facts
Patent No.
US 10,383,228
App. No.
16/116,156
Granted
Aug 13, 2019
Kind
B2
Abstract

An electronic component device includes a first coreless wiring substrate, an electronic component mounted on the first coreless wiring substrate, a second coreless wiring substrate disposed above the first coreless wiring substrate and the electronic component such that the second coreless wiring substrate is spaced from the first coreless wiring substrate and the electronic component, a connection terminal that connects the first coreless wiring substrate and the second coreless wiring substrate, and a sealing resin filled between the first and second coreless wiring substrates. Each of the first and second coreless wiring substrates include an insulating layer, a wiring layer, and a reinforcing layer embedded in the insulating layer and provided in a region overlaying the electronic component.

Claims (63)

1. An electronic component device comprising:

a first coreless wiring substrate;

an electronic component that is mounted on the first coreless wiring substrate;

a second coreless wiring substrate that is disposed above the first coreless wiring substrate and the electronic component such that the second coreless wiring substrate is spaced from the first coreless wiring substrate and the electronic component;

a connection terminal that connects the first coreless wiring substrate and the second coreless wiring substrate; and

a sealing resin that is filled between the first and second coreless wiring substrates,

wherein the first coreless wiring substrate comprises a first insulating layer, a first wiring layer, and a first reinforcing layer that is embedded in the first insulating layer and provided in a region overlaying the electronic component,

wherein the first insulating layer comprises a first surface and a second surface opposite to the first surface, the first surface of the first insulating layer being opposed to the electronic component, the second surface of the first insulating layer being flush with a surface of the first reinforcing layer, and the second surface of the first insulating layer and the surface of the first reinforcing layer being exposed to an outside of the electronic component device, and

wherein the second coreless wiring substrate comprises a second insulating layer, a second wiring layer, and a second reinforcing layer that is embedded in the second insulating layer and provided in a region overlaying the electronic component.

2. The device of claim 1 , wherein each reinforcing layer comprises one selected from the group consisting of

(i) a structure in which a copper layer, a nickel layer, a palladium layer, and a gold layer are stacked in order from an electronic component side,

(ii) a structure in which a copper layer, a nickel layer, and a gold layer are stacked in order from the electronic component side, and

(iii) a structure in which a copper layer and a nickel layer are stacked in order from the electronic component side.

3. The device of claim 1 , wherein

the second insulating layer comprises a first surface and a second surface opposite to the first surface, the first surface being opposed to the electronic component, and

a distance between the electronic component and the first surface of the second insulating layer is equal to or larger than 30 μm.

4. The device of claim 1 , wherein:

the first coreless wiring substrate further comprises a first via conductor formed in the first insulating layer,

the second coreless wiring substrate further comprises a second via conductor formed in the second insulating layer, and

each of the first and second via conductors has a truncated cone shape whose diameter is smaller on an outer side of the electronic component device than on an inner side of the electronic component device.

5. The device of claim 1 , wherein the connection terminal comprises a metal pillar.

6. The device of claim 1 , wherein

the second insulating layer comprises a first surface and a second surface opposite to the first surface, the first surface being opposed to the electronic component, and

the second surface of the second insulating layer is flush with a surface of the second reinforcing layer, and the second surface of the second insulating layer and the surface of the second reinforcing layer are exposed to an outside of the electronic component device.

7. The device of claim 6 , wherein:

the first coreless wiring substrate further comprises a first via conductor formed in the first insulating layer and a first pad formed on the second surface of the first insulating layer, the first via conductor connecting the first wiring layer and the first pad, and

the second coreless wiring substrate further comprises a second via conductor formed in the second insulating layer and a second pad formed on the second surface of the second insulating layer, the second via conductor connecting the second wiring layer and the second pad.

8. The device of claim 1 , wherein at least one of the first reinforcing layer and the second reinforcing layer is formed with a plurality of holes defined therein.

9. The device of claim 1 , wherein the connection terminal is a solder ball having a core.

10. The device of claim 1 , wherein a surface of the first wiring layer is exposed from the second surface of the first insulating layer.

11. The device of claim 1 , wherein the second insulating layer comprises a first surface and a second surface opposite to the first surface, the first surface being opposed to the electronic component, and a surface of the second wiring layer being exposed from the second surface of the second insulating layer.

12. The device of claim 11 , wherein:

the first coreless wiring substrate further comprises a first via conductor formed in the first insulating layer and a first pad formed on the second surface of the first insulating layer, the first via conductor connecting the first wiring layer and the first pad, and

the second coreless wiring substrate further comprises a second via conductor formed in the second insulating layer and a second pad formed on the second surface of the second insulating layer, the second via conductor connecting the second wiring layer and the second pad.

13. The device of claim 1 , wherein:

the first coreless wiring substrate further comprises a first via conductor formed in the first insulating layer and a first pad formed on the second surface of the first insulating layer, the first via conductor connecting the first wiring layer and the first pad.

14. An electronic component device comprising:

a first coreless wiring substrate;

an electronic component that is mounted on the first coreless wiring substrate;

a second coreless wiring substrate that is disposed above the first coreless wiring substrate and the electronic component such that the second coreless wiring substrate is spaced from the first coreless wiring substrate and the electronic component;

a connection terminal that connects the first coreless wiring substrate and the second coreless wiring substrate; and

a sealing resin that is filled between the first and second coreless wiring substrates,

wherein the first coreless wiring substrate comprises a first insulating layer, a first wiring layer, and a first reinforcing layer that is embedded in the first insulating layer and provided in a region overlaying the electronic component,

wherein the second coreless wiring substrate comprises a second insulating layer, a second wiring layer, and a second reinforcing layer that is embedded in the second insulating layer and provided in a region overlaying the electronic component, and

wherein the second insulating layer comprises a first surface and a second surface opposite to the first surface, the first surface of the second insulating layer being opposed to the electronic component, the second surface of the second insulating layer being flush with a surface of the second reinforcing layer, and the second surface of the second insulating layer and the surface of the second reinforcing layer being exposed to an outside of the electronic component device.

15. The device of claim 14 , wherein each reinforcing layer comprises one selected from the group consisting of

(i) a structure in which a copper layer, a nickel layer, a palladium layer, and a gold layer are stacked in order from an electronic component side,

(ii) a structure in which a copper layer, a nickel layer, and a gold layer are stacked in order from the electronic component side, and

(iii) a structure in which a copper layer and a nickel layer are stacked in order from the electronic component side.

16. The device of claim 14 , wherein a distance between the electronic component and the first surface of the second insulating layer is equal to or larger than 30 μm.

17. The device of claim 14 , wherein:

the first coreless wiring substrate further comprises a first via conductor formed in the first insulating layer,

the second coreless wiring substrate further comprises a second via conductor formed in the second insulating layer, and

each of the first and second via conductors has a truncated cone shape whose diameter is smaller on an outer side of the electronic component device than on an inner side of the electronic component device.

18. The device of claim 14 , wherein the connection terminal comprises a metal pillar.

19. The device of claim 14 , wherein at least one of the first reinforcing layer and the second reinforcing layer is formed with a plurality of holes defined therein.

20. The device of claim 14 , wherein the connection terminal is a solder ball having a core.

21. The device of claim 14 , wherein the first insulating layer comprises a first surface and a second surface opposite to the first surface, the first surface of the first insulating layer being opposed to the electronic component, and a surface of the first wiring layer being exposed from the second surface of the first insulating layer.

22. The device of claim 21 , wherein:

the first coreless wiring substrate further comprises a first via conductor formed in the first insulating layer and a first pad formed on the second surface of the first insulating layer, the first via conductor connecting the first wiring layer and the first pad.

23. The device of claim 14 , wherein a surface of the second wiring layer is exposed from the second surface of the second insulating layer.

24. The device of claim 14 , wherein:

the second coreless wiring substrate further comprises a second via conductor formed in the second insulating layer and a second pad formed on the second surface of the second insulating layer, the second via conductor connecting the second wiring layer and the second pad.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2018
From: KYOZUKA, MASAHIRO
To: SHINKO ELECTRIC INDUSTRIES CO., LTD.
Reel/Frame 046741/0663 →
Priority Claims (1)
JP 2014-170410 · Aug 25, 2014 · national
Continuity (2)
Division 14833578 · Aug 24, 2015
Related Publication 20190029113A1 · Jan 24, 2019