Systems and methods for bypass testing
Technology for bypass testing of an integrated circuit using a testing device. The testing device comprising a port configured to connect to an integrated circuit before the integrated circuit is packaged into an end product. The testing device further comprising a controller with architecture configured to bypass a training process designed to be initiated when the integrated circuit is first connected to the port and the port is powered on, confirm a connection between the integrated circuit and the testing device, send a test pattern to the integrated circuit to execute; and receive results from the integrated circuit executing the test pattern.
1. A testing device for testing an integrated circuit, comprising:
a port configured to connect to an integrated circuit before the integrated circuit is packaged into an end product; and
a controller with architecture configured to:
bypass a training process designed to be initiated when the integrated circuit is first connected to the port and the port is powered on;
confirm a connection between the integrated circuit and the testing device;
send a test pattern to the integrated circuit to execute; and
receive results from the integrated circuit executing the test pattern;
wherein the training process comprises at least one of low frequency periodic signaling (LFPS), a polling substate, an RxDetect state, or a synchronization point.
2. The testing device as recited in claim 1 , wherein the test pattern comprises a plurality of test patterns.
3. The testing device as recited in claim 2 , wherein at least one of the plurality of test patterns is configured to test the training process.
4. The testing device as recited in claim 1 , wherein the testing device comprises a plurality of ports for testing a plurality of integrated circuits.
5. The testing device as recited in claim 1 , wherein the test pattern is generated by a test access mechanism (TAM) DFx.
6. The testing device as recited in claim 1 , wherein the controller is further configured to bypass a plurality of training processes.
7. The testing device as recited in claim 1 , wherein the controller is configured to optionally bypass or not bypass the training process.
8. The testing device as recited in claim 1 , wherein the port is selected from the group of ports consisting of: a universal serial bus (USB) 3 port, a serial ATA (SATA) port, and a peripheral component interconnect express (PCIe) port.
9. The testing device as recited in claim 1 , wherein the controller is a link training and status state machine with specific purpose hardware.
10. The testing device as recited in claim 1 , wherein the controller interfaces with the port via a pipe gasket.
11. The testing device as recited in claim 1 , wherein the connection is confirmed between the integrated circuit and the testing device via a pipe signal handshake.
12. The testing device as recited in claim 1 , wherein the connection is confirmed between the integrated circuit and the testing device via a polling config stage.
13. The testing device as recited in claim 1 , wherein the port is an input/output port.
14. The testing device as recited in claim 1 , wherein the controller is further configured to power on the port and control the port before the training process is bypassed.
15. A method for testing an integrated circuit, comprising:
bypassing a training process designed to be initiated when an integrated circuit is first connected to a port of a testing device and the port is powered on;
confirming a connection between the integrated circuit and the testing device via a controller of the testing device;
sending a test pattern to the integrated circuit to execute; and
receiving results from the integrated circuit executing the test pattern;
wherein the training process comprises at least one of low frequency periodic signaling (LFPS), a polling substate, or an RxDetect state.
16. The method as recited in claim 15 , wherein the test pattern comprises a plurality of test patterns.
17. The method as recited in claim 15 , wherein the test pattern is generated by a test access mechanism (TAM) DFx.
18. The method as recited in claim 15 , wherein the bypassing comprises bypassing a plurality of training processes.
19. The method as recited in claim 15 , wherein the controller is a link training and status state machine with specific purpose hardware.
20. The method as recited in claim 15 , wherein the confirming the connection between the integrated circuit and the testing device is accomplished via a pipe signal handshake.
21. The method as recited in claim 15 , wherein the confirming the connection between the integrated circuit and the testing device is accomplished via a polling config stage.