IP Library Granted Patent US 11,069,702
Granted Patent B2
US 11,069,702 · App. 16/116,814 · Granted Jul 20, 2021

Semiconductor device and manufacturing method thereof

Inventor: Hiroyasu Sato (Yokkaichi Mie, JP)
Assignee: TOSHIBA MEMORY CORPORATION
H01L27/11582H01L21/0262H01L21/02532H01L21/26513H01L21/31116H01L21/324H01L27/11519H01L27/11556H01L27/11565H01L29/105H01L29/1037H01L29/167H01L29/40114H01L29/40117H01L29/7883H01L29/7889H01L29/7926H01L21/02592H01L21/02595H01L21/02667H01L21/31053
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Quick Facts
Patent No.
US 11,069,702
App. No.
16/116,814
Granted
Jul 20, 2021
Kind
B2
Abstract

According to one embodiment, a semiconductor device includes a substrate, a stack comprising a plurality of conductive layers stacked one over the other in a first direction, and an insulating layer interposed between adjacent conductive layers located over the substrate, a first semiconductor layer extending inwardly of the stack and through the plurality of conductive layers in the first direction, a memory layer located between the first semiconductor layer and the plurality of conductive layers, and a second semiconductor layer located over, and in contact with, the first semiconductor layer, wherein the second semiconductor layer includes a third semiconductor layer containing phosphorous, and a fourth semiconductor layer containing carbon provided between the first semiconductor layer and the third semiconductor layer.

Claims (19)

1. A semiconductor device comprising:

a stack comprising a plurality of conductive layers stacked and separated from each other in a first direction;

an insulating layer provided above the stack;

a columnar portion extending through the plurality of conductive layers and the insulating layer in the first direction;

wherein the columnar portion includes a core layer extending through at least one of the conductive layers in the first direction, a first semiconductor layer located between the core layer and the plurality of conductive layers, a memory layer located between the first semiconductor layer and the plurality of conductive layers, and a second semiconductor layer that is located above the core layer and contacts the first semiconductor layer, and

wherein the second semiconductor layer includes a first region containing phosphorous, and a second region that contains carbon and phosphorous, and

the second region includes a first sub-region provided between the core layer and the first region of the second semiconductor layer in the first direction and a second sub-region provided between the insulating layer and the first region of the second semiconductor layer.

2. The semiconductor device according to claim 1 , wherein the first semiconductor layer contains carbon, and a carbon concentration in the first semiconductor layer is lower than a carbon concentration in the second region of the second semiconductor layer.

3. The semiconductor device according to claim 2 , wherein the carbon concentration in the first semiconductor layer decreases along the first direction as being distant away from the first sub-region of the second semiconductor layer.

4. The semiconductor device according to claim 1 , wherein the first region of the second semiconductor layer contains carbon, and a carbon concentration in the first region of the second semiconductor layer is lower than a carbon concentration in the second region of the second semiconductor layer.

5. The semiconductor device according to claim 4 , wherein the carbon concentration in the first region of the second semiconductor layer decreases in the first direction as being distant away from the first sub-region of the second semiconductor layer.

6. The semiconductor device according to claim 1 , further comprising a contact contacting the second semiconductor layer.

7. The semiconductor device according to claim 1 , wherein

the stack is provided on a substrate, and

a lowermost surface of the second semiconductor layer is farther from the substrate in the first direction than is an upper surface of the uppermost one of the conductive layers in the stack from the substrate in the first direction.

8. The semiconductor device according to claim 1 , wherein the carbon concentration in the first region of the second semiconductor layer decreases along a second direction that is perpendicular to the first direction as being distant away from the second sub-region of the second semiconductor layer.

9. The semiconductor device according to claim 1 , wherein a side surface of the second sub-region of the second semiconductor layer is in contact with the first semiconductor layer.

10. The semiconductor device according to claim 1 , wherein a side surface of the second sub-region of the second semiconductor layer is in contact with the memory layer.

11. The semiconductor device according to claim 1 , wherein a bottom surface of the second sub-region of the second semiconductor layer is in contact with the first semiconductor layer.

Assignments (4)
CHANGE OF NAME AND ADDRESS Recorded Feb 4, 2022
From: K.K PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 058957/0124 →
CHANGE OF NAME AND ADDRESS Recorded Jan 31, 2022
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 058905/0582 →
MERGER Recorded Jan 31, 2022
From: TOSHIBA MEMORY CORPORATION
To: K.K PANGEA
Reel/Frame 058946/0675 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 25, 2018
From: SATO, HIROYASU
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 047312/0759 →
Priority Claims (1)
JP JP2018-047132 · Mar 14, 2018 · national
Continuity (1)
Related Publication 20190287992A1 · Sep 19, 2019