Integrated circuit memory devices with enhanced buffer memory utilization during read and write operations and methods of operating same
View Patent ↗An integrated circuit device includes a nonvolatile memory, first and second buffer memories, and a controller. Each of the first and second buffer memories is configured to buffer write data to be written to the nonvolatile memory in response to a write request and also buffer read data received from the nonvolatile memory in response to a read request. A controller is provided, which evaluates the first buffer memory against at least one criterion relating to data accuracy. The controller is configured to: redirect at least some of the write data from the first buffer memory to the second buffer memory in response to the write request when the evaluation demonstrates the criterion has been exceeded, and redirect at least some of the read data from the first buffer memory to the second buffer memory in response to the read request when the evaluation demonstrates the criterion has been exceeded.
1. A storage device comprising:
a nonvolatile memory; and
a controller comprising a buffer memory and a read-only memory;
wherein the buffer memory includes volatile memory cells, and is configured to buffer write data to be written into the nonvolatile memory and buffer read data read from the nonvolatile memory;
wherein the read-only memory includes volatile memory cells, and is configured to store metadata for performing a control operation of the controller; and
wherein the controller is configured to: (i) monitor the number of error bits generated in the buffer memory or a generation frequency of the error bits when the buffer memory is buffering write data and/or read data, (ii) dynamically determine a refresh cycle rate with respect to the read-only memory as a function of the number of error bits generated in the buffer memory or the generation frequency of the error bits and not as a function of the number of error bits in the metadata within the read-only memory, and (iii) dynamically control a refresh operation with respect to the read-only memory according to the determined refresh cycle.
2. The storage device of claim 1 , wherein the controller further comprises a rewrite manager configured to compare the number of error bits or the generation frequency of the error bits to a threshold value, decrease the refresh cycle when the number of error bits or the generation frequency of the error bits is equal to or higher than the threshold value, and increase the refresh cycle when the number of error bits or the generation frequency of the error bits is lower than the threshold value.
3. The storage device of claim 1 , wherein the nonvolatile memory comprises a meta area in which the metadata written on the read-only memory is stored, and
the controller is further configured to rewrite the metadata stored in the meta area on the read-only memory according to the determined refresh cycle.
4. The storage device of claim 1 , wherein the controller further comprises a monitoring module configured to monitor the number of error bits or the generation frequency of the error bits by comparing data input to the buffer memory and data output from the buffer memory.
5. The storage device of claim 1 , wherein the controller further comprises an error check and correction module configured to perform an error check and correction operation with respect to data buffered into the buffer memory.
6. The storage device of claim 1 , wherein the controller is further configured to monitor an input/output speed of the write data or the read data, and dynamically determine the refresh cycle rate based on the input/output speed.