DFE open loop training for DDR data buffer and registered clock driver

1. An apparatus comprising:

an interface configured to transmit signals to/from a plurality of I/O channels; and

a training circuit configured to (i) generate a training voltage signal comprising a pulse on a current one of said I/O channels, (ii) read an output of an eye monitor slicer to determine voltage transition values corresponding to said training voltage signal at a plurality of sampling times, (iii) map said voltage transition values to coefficients for said current I/O channel, and (iv) determine said coefficients for each of said I/O channels, wherein (a) said training circuit comprises said eye monitor slicer and a multiplexer circuit, (b) said voltage transition values correspond to an interference response for said current I/O channel, (c) said coefficients are applied as feedback to cancel said interference, (d) said training voltage signal comprises a single bit in a first state followed by a string of bits in a second state, (e) in a training mode said multiplexer circuit allows said output of said eye monitor to be read directly to determine said voltage transition values, and (f) in a mission mode said multiplexer circuit presents a difference between said output of said eye monitor slicer and an output of a DO slicer to handle errors from said DQ slicer.

2. The apparatus according to claim 1 , wherein said training voltage signal is applied to determine a single bit response of said current I/O channel.

3. The apparatus according to claim 1 , wherein said string of bits in said second state is longer than the sampling times corresponding to a number of DFE taps.

4. The apparatus according to claim 1 , wherein (a) a DC level for said current I/O channel is determined before determining said voltage transition values and (b) said voltage transition values are referenced to said DC level.

5. The apparatus according to claim 1 , wherein said training circuit determines said coefficients in a first mode of operation of a memory circuit and said coefficients are applied in a second mode of operation of said memory circuit.

6. The apparatus according to claim 1 , wherein said coefficients are updated in response to a change in at least one of an operation voltage, a temperature and a data rate.

7. The apparatus according to claim 1 , wherein said apparatus generates said coefficients using an open loop training approach.

8. The apparatus according to claim 1 , wherein said interface and said training circuit are implemented in a data buffer of a memory circuit.

9. The apparatus according to claim 1 , wherein said interface and said training circuit are implemented in a registered clock driver of a memory circuit.

10. The apparatus according to claim 1 , wherein said coefficients are decision feedback equalizer (DFE) tap coefficients.

11. The apparatus according to claim 1 , wherein said interference response is an intersymbol interference (ISI).

12. The apparatus according to claim 1 , wherein said interference response is caused by bandwidth limitations in said I/O channels and reflections.

13. The apparatus according to claim 1 , wherein (i) said coefficients improve a receiver eye margin for said signals and (ii) said signals comprise one or more of (a) data signals and (b) command/address signals.

14. The apparatus according to claim 1 , wherein respective coefficients are obtained for each of said I/O channels by independently training each of said I/O channels based on system settings.

15. The apparatus according to claim 1 , wherein said training circuit determines said coefficients during a power on self test of a computing device.

16. The apparatus according to claim 1 , wherein said voltage transition values determined at said sampling times correspond to post-cursor values.