Granted Patent B2

US 10,630,170 · App. 16/117,341 · Granted Apr 21, 2020

Abstract

Claims (59)

1. A Power Factor Correction (PFC) circuit, the PFC circuit comprising:

an oscillator circuit to:

receive a valley detect signal indicating a zero current condition;

determine a blanking time according to an operational cycle of the PFC circuit; and

determine to initiate the operational cycle of the PFC circuit according to the valley detect signal and the blanking time;

a first feedback loop circuit to determine, according to an output voltage of the PFC circuit, a first duration of a charging period of the operational cycle; and

a second feedback loop circuit to determine a delay time having a value determined according to zero current times of one or more previous operational cycles and to extend the first duration of the charging period by the delay time,

wherein the second feedback loop circuit has a higher bandwidth than the first feedback loop circuit.

2. The PFC circuit of claim 1 , wherein respective zero current times of the one or more previous operational cycles correspond to durations from respective first assertion of the valley detect signal to respective initiations of the next operational cycle.

3. The PFC circuit of claim 1 ,

wherein the PFC circuit operates in a Boundary Conduction Mode (BCM) when a duration of a charge-discharge period of the operational cycle is greater than the blanking time, and

wherein the PFC circuit operates in a Discontinuous Conduction Mode (DCM) when the duration of a charge-discharge period of the operational cycle is less than the blanking time.

4. The PFC circuit of claim 3 , wherein the delay time is zero when the PFC circuit operates in BCM and is greater than zero when the PFC circuit operates in DCM.

5. The PFC circuit of claim 1 , wherein a first control signal is generated by the first feedback loop circuit and has a first pulse that is asserted for a duration corresponding to the first duration, the PFC circuit further comprising:

a turn off delay circuit included in the second feedback loop circuit, the turn off delay circuit to receive the first control signal and to:

assert a second control signal immediately in response to an assertion of the first control signal; and

de-assert the second control signal after the delay time in response to a de-assertion of the first control signal.

6. The PFC circuit of claim 1 , wherein the oscillator circuit determines to initiate the operational cycle in response to the valley detect signal indicating the zero current condition after a blanking time of an immediately previous operational cycle has expired.

7. The PFC circuit of claim 1 , wherein the blanking time begins at the time the operational cycle is initiated.

8. A method for controlling a PFC circuit, the method comprising:

producing a valley detect signal indicating a zero current condition;

determining a blanking time according to an operational cycle of the PFC circuit;

determine to initiate the operational cycle of the PFC circuit according to the valley detect signal and the blanking time;

determining, according to an output voltage of the PFC circuit, a first duration of a charging operation of the operational cycle;

determining a delay time having a value determined according to zero current times of one or more previous operational cycles;

extending the first duration of the charging operation by the delay time;

determining the first duration using a first feedback loop circuit having a first bandwidth; and

determining the delay time using a second feedback loop circuit having a second bandwidth,

wherein the second bandwidth is greater than the first bandwidth.

9. The method of claim 8 , further comprising determining a zero current time of a previous operation cycle of the one or more previous operational cycles according to time of a first occurrence of the zero current condition in the previous operation cycle and a time of initiation of the operational cycle immediately following the previous operation cycle.

10. The method of claim 8 , further comprising:

operating the PFC circuit in a Boundary Conduction Mode (BCM) when a duration of a charge-discharge period of the operational cycle is greater than the blanking time, and

operating the PFC circuit in a Discontinuous Conduction Mode (DCM) when the duration of a charge-discharge period of the operational cycle is less than the blanking time.

11. The method of claim 10 , wherein the delay time is zero when the PFC circuit operates in BCM and is greater than zero when the PFC circuit operates in DCM.

12. The method of claim 8 , further comprising:

generating a first control signal having a first pulse that is asserted for a duration corresponding to the first duration;

asserting a second control signal immediately in response to an assertion of the first control signal;

de-assert the second control signal after the delay time in response to a de-assertion of the first control signal; and

performing the charging operation when the second control signal is asserted.

13. The method of claim 8 , further comprising:

determining to initiate the operational cycle in response to the valley detect signal indicating the zero current condition after a blanking time of an immediately previous operational cycle has expired.

14. The method of claim 8 , wherein the blanking time begins at the time the operational cycle is initiated.

15. A Power Factor Correction (PFC) circuit, the PFC circuit comprising:

a current sense circuit to generate a current sense signal according to a sensed current;

a zero current detector circuit to generate a valley detect signal using the current sense signal;

an oscillator circuit to receive the valley detect signal, determine a blanking time according to an operational cycle of the PFC circuit, and generate an on trigger signal according to the valley detect signal and the blanking time;

a first feedback loop circuit to determine a first duration of a gate control signal according to an output voltage of the PFC circuit; and

a second feedback loop circuit to determine a delay time having a value determined according to a duty cycle of the sensed current,

wherein the PFC circuit initiates a charging operation in response to an assertion of the on trigger signal, and terminates the charging operation after the delay time has elapsed after the first duration has elapsed after initiating the charging operation, and

wherein the second feedback circuit has a higher bandwidth than the first feedback circuit.

16. The PFC circuit of claim 15 , wherein the second feedback circuit comprises:

a zero current indicator circuit to assert a zero current time signal in response to the valley detect signal being asserted and de-assert the zero current time signal in response to the charging operation being initiated;

a low-pass filter circuit to produce a zero current voltage signal by low-pass filtering the zero current time signal; and

a delay time circuit to generate the delay time according to the zero current voltage signal.

17. The PFC circuit of claim 15 , further comprising:

a first latch circuit to assert a switch control signal in response to the assertion of the on trigger signal and de-assert the switch control signal in response to the assertion of an off trigger signal;

an off trigger generator circuit to assert the off trigger signal in response to the first duration elapsing after the assertion of the switch control signal; and

a second latch circuit to assert a modified switch control signal in response to the assertion of the switch control signal and to de-assert the modified switch control signal in response to the delay time elapsing after the switch control signal is de-asserted,

wherein the charging operation is initiated in response to the assertion of the modified switch control signal and terminated in response to the de-assertion of the modified switch control signal.

Assignments (7)