Semiconductor structure and fabrication method thereof

1. A method for fabricating a semiconductor structure, comprising:

providing a substrate, wherein the substrate includes an active region and a blank region disposed adjacent to the active region;

forming a fin material layer on the substrate and a hard mask material layer on the fin material layer; and

sequentially forming a hard mask on the fin material layer and forming a plurality of fins on the active region, and a plurality of dummy fins on the blank region by etching the hard mask material layer and the fin material layer using a plurality of fin patterns over the active region, and a plurality of dummy fin patterns over the blank region as a same mask, wherein a spacing between a fin and an adjacent dummy fin is greater than a spacing between adjacent fins, wherein:

a spacing between a fin pattern and an adjacent dummy fin pattern is greater than a spacing between adjacent fin patterns,

forming the plurality of fin patterns and the plurality of dummy fin patterns includes: a double patterning process, and

forming the plurality of fin patterns and the plurality of dummy fin patterns includes:

forming a plurality of core patterns over the fin material layer,

wherein:

the plurality of core patterns are disposed on both the active region and the blank region,

when a boundary position between the active region and the blank region corresponds to a position of one core pattern, a line width of the one core pattern over the boundary position between the active region and the blank region is greater than a line width of a core pattern over the active region, and

when the boundary position between the active region and the blank region corresponds to a position of a gap between adjacent core patterns, a width of the gap between the adjacent core patterns over the boundary position between the active region and the blank region is greater than a width of a gap between adjacent core patterns over the active region;

forming the plurality of fin patterns on sidewalls of the core patterns over the active region, and the plurality of dummy fin patterns on sidewalls of the core patterns over the blank region; and

removing the plurality of core patterns.

2. The method according to claim 1 , wherein forming the plurality of core patterns includes:

forming a core material layer over the fin material layer, and a plurality of photolithography patterns on the core material layer; and

patterning the core material layer using the plurality of photolithography patterns as a mask to form the plurality of core patterns.

3. The method according to claim 2 , after forming the core material layer and before forming the plurality of photolithography patterns, further including:

forming a first anti-reflective layer on the core material layer.

4. The method according to claim 1 , wherein:

a ratio of the spacing between the fin and the adjacent dummy fin over the spacing between the adjacent fins is in a range of approximately 1-2.

5. The method according to claim 1 , wherein:

the spacing between the fin and the adjacent dummy fin is in a range of approximately 25 nm-50 nm.

6. The method according to claim 1 , wherein:

the spacing between the adjacent fins is in a range of approximately 25 nm-30 nm.

7. A method for fabricating a semiconductor structure, comprising:

providing a substrate, wherein the substrate includes an active region and a blank region disposed adjacent to the active region;

forming a fin material layer on the substrate; and

forming a plurality of fins on the active region, and a plurality of dummy fins on the blank region by etching the fin material layer, wherein a spacing between a fin and an adjacent dummy fin is greater than a spacing between adjacent fins, wherein forming the plurality of fins and the plurality of dummy fins includes:

forming a plurality of fin patterns over the active region, and a plurality of dummy fin patterns over the blank region, wherein a spacing between a fin pattern and an adjacent dummy fin pattern is greater than a spacing between adjacent fin patterns;

etching the fin material layer using the plurality of fin patterns and the plurality of dummy fin patterns as a mask to form the plurality of fins and the plurality of dummy fins;

removing the plurality of dummy fins to expose the blank region of the substrate;

forming a dielectric layer on the substrate exposed by the plurality of fins; and

removing a thickness portion of the dielectric layer along a direction perpendicular to a surface of the substrate to partially expose sidewall surfaces of the plurality of fins.

8. The method according to claim 7 , wherein removing the dummy fins includes:

forming a filling layer on the substrate exposed by the plurality of fins and the plurality of dummy fins;

forming a protection layer on a surface of the filling layer over the active region; and

removing the plurality of dummy fins by etching using the protection layer as a mask to expose the blank region of the substrate.

9. The method according to claim 7 , wherein forming the dielectric layer includes:

a fluid chemical vapor deposition process.

10. The method according to claim 7 , wherein forming the dielectric layer includes:

forming a flowable precursor material on the substrate exposed by the plurality of fins; and

curing the precursor material by performing an annealing treatment, wherein the cured precursor material forms the dielectric layer.

11. The method according to claim 10 , wherein parameters of the annealing treatment include:

an annealing temperature in a range of approximately 400° C.-1050° C.; and

an annealing time in a range of approximately 30 minutes-300 minutes.

12. The method according to claim 7 , wherein:

a ratio of the spacing between the fin and the adjacent dummy fin over the spacing between the adjacent fins is in a range of approximately 1-2.

13. The method according to claim 7 , wherein:

the spacing between the fin and the adjacent dummy fin is in a range of approximately 25 nm-50 nm.

14. The method according to claim 7 , wherein:

the spacing between the adjacent fins is in a range of approximately 25 nm-30 nm.

15. The method according to claim 14 , after forming the core material layer and before forming the plurality of photolithography patterns, further including:

forming a first anti-reflective layer on the core material layer.

16. The method according to claim 7 , wherein forming the plurality of fin patterns and the plurality of dummy fin patterns includes:

a double patterning process.

17. The method according to claim 16 , wherein forming the plurality of fin patterns and the plurality of dummy fin patterns includes:

forming a plurality of core patterns over the fin material layer,

wherein:

the plurality of core patterns are disposed on both the active region and the blank region,

when a boundary position between the active region and the blank region corresponds to a position of one core pattern, a line width of the one core pattern over the boundary position between the active region and the blank region is greater than a line width of a core pattern over the active region, and

when the boundary position between the active region and the blank region corresponds to a position of a gap between adjacent core patterns, a width of the gap between the adjacent core patterns over the boundary position between the active region and the blank region is greater than a width of a gap between adjacent core patterns over the active region;

forming the plurality of fin patterns on sidewalls of the core patterns over the active region, and the plurality of dummy fin patterns on sidewalls of the core patterns over the blank region; and

removing the plurality of core patterns.