Fabrication method for fin-based semiconductor device
Semiconductor device and fabrication method are provided. The method includes: providing a semiconductor substrate; forming initial fins on the semiconductor substrate; forming a gate structure material layer on the semiconductor substrate and the initial fins, the gate material layer having a top surface higher than the initial fins; forming a trench in the gate structure material layer and the initial fins, which passes through the initial fins along a direction perpendicular to an extending direction of initial fins and in parallel with a surface of the semiconductor substrate to form initial fins into fins; forming an isolation layer in the trench having a top surface higher than the fins; and forming gate structures on both sides of the isolation layer by etching the gate structure material layer.
1. A fabrication method of a semiconductor device, comprising:
providing a semiconductor substrate;
forming initial fins on the semiconductor substrate;
forming a gate structure material layer on the semiconductor substrate and the initial fins, wherein the gate structure material layer has a top surface higher than the initial fins;
forming a trench in the gate structure material layer and the initial fins, the trench passing through the initial fins along a direction perpendicular to an extending direction of initial fins and in parallel with a surface of the semiconductor substrate, wherein fins are formed from the initial fins by the trench, and a top size of the trench in the gate structure material layer is larger than a bottom size of the trench in the fins along an extending direction of the fins;
forming an isolation layer in the trench, wherein the isolation layer has a top surface higher than the fins; and
after forming the isolation layer in the trench, forming gate structures on both sides of the isolation layer by etching the gate structure material layer.
2. The fabrication method according to claim 1 , further including:
forming a mask layer on the gate structure material layer before forming the trench, wherein the mask layer has an opening;
forming the trench by etching the gate structure material layer and the initial fins along the opening using the mask layer as a mask;
etching the mask layer to form a gate protection layer after forming the isolation layer and before etching the gate structure material layer; and
forming the gate structures by etching the gate structure material layer using the gate protection layer as a mask, wherein the gate protection layer is formed on the gate structures.
3. The fabrication method according to claim 2 , wherein:
forming the isolation layer includes: forming an isolation film in the opening and the trench, and on the mask layer; and forming the isolation layer by planarizing the isolation film to expose the mask layer.
4. The fabrication method according to claim 2 , wherein:
etching the gate structure material layer and initial fins along the opening using the mask layer as a mask includes:
a first anisotropic dry etching process for etching the gate structure material layer and initial fins along the opening using the mask layer as a mask thereby forming an initial trench in the gate structure material layer and the initial fins;
a second anisotropic dry etching process, following the first anisotropic dry etching process, for etching the initial fins at a bottom of the initial trench using the mask layer as a mask, thereby forming the trench from the initial trench and forming the fins from the initial fins.
5. The fabrication method according to claim 4 , further including:
in the first anisotropic dry etching process:
a gas including CH 4 , CHF 3 , Ar, He, or a combination thereof;
a flow rate of CH 4 of 50 sccm to 200 sccm;
a flow rate of CHF 3 of 50 sccm to 300 sccm;
a flow rate of Ar of 200 sccm to 500 sccm;
a flow rate of He of 200 sccm to 500 sccm;
a source RF having a power of 200 W to 1000 W;
a bias voltage of 200 V to 1000 V; and
a chamber pressure of 10 mtorr to 50 mtorr.
6. The fabrication method according to claim 4 , further including:
in the second anisotropic dry etching process:
a gas including O 2 , N 2 , HBr, or a combination thereof;
a flow rate of O 2 of 3 sccm to 10 sccm;
a flow rate of N 2 of 10 sccm to 30 sccm;
a flow rate of HBr of 200 sccm to 500 sccm;
a source RF power of 500 W to 1000 W;
a bias voltage of 200 V to 700 V; and
a chamber pressure of 20 mtorr to 80 mtorr.
7. The fabrication method according to claim 1 , further including:
before forming the isolation layer, forming a barrier layer on sidewalls and a bottom of the trench, and
forming the isolation layer on the barrier layer.
8. The fabrication method according to claim 7 , wherein:
the barrier layer is made of a material including silicon nitride.
9. The fabrication method according to claim 7 , wherein:
a thickness of the barrier layer is 5 Angstroms to 10 Angstroms.
10. The fabrication method according to claim 1 , further including:
before forming the gate structure material layer, forming an isolation structure covering a portion of sidewalls of the initial fins on the semiconductor substrate, wherein after forming the fins, the isolation structure covers a portion of sidewalls of the fins, the gate structure material layer is on the isolation structure, and the gate structures is also on the isolation structure after forming the gate structures.
11. The fabrication method according to claim 10 , wherein:
the isolation structure is made of a material including silicon dioxide.
12. The fabrication method according to claim 10 , wherein:
the trench passed through the isolation structure.
13. The fabrication method according to claim 1 , wherein:
the isolation layer is formed on a top surface of the semiconductor substrate.
14. The fabrication method according to claim 1 , wherein:
the isolation layer is made of a material including silicon dioxide.
15. The fabrication method according to claim 1 , wherein:
the gate structure material layer includes a gate dielectric material layer on the semiconductor substrate and the initial fins, and a gate material layer on the gate dielectric material layer.
16. The fabrication method according to claim 15 , wherein:
the gate dielectric material layer is made of a material including silicon dioxide; and
the gate material layer is made of a material including polycrystalline silicon.
17. The fabrication method according to claim 1 , further including:
forming the source/drain doped regions in the fins on each side of the gate structure; and
forming the source/drain doped regions in the fins between the isolation layer and the gate structure.
18. The fabrication method according to claim 17 , further including:
forming the first spacers on sidewalls of each gate structure and the second spacers covering a portion of the fins on sidewalls of the isolation layer, wherein the source/drain doped regions are in the fins of gate structures and on each side of the first spacers.
19. The fabrication method according to claim 1 , wherein:
a top size of the trench in the fins equals the top size of the trench in the gate structure material layer and is larger than a bottom size of the trench in the fins along an extending direction of the fins.
20. The fabrication method according to claim 1 , wherein:
each sidewall of the trench has a single step in the fins.