Semiconductor memory

1. A semiconductor memory comprising:

a first plane that includes a first memory cell array;

a second plane that includes a second memory cell array; and

a control circuit that includes a first circuit configured to store a first priority for a first operation performed on the first plane, a second circuit configured to store a second priority for a second operation performed on the second plane, a first sequencer circuit for the first plane, and a second sequencer circuit for the second plane, and is configured to control the first and second operations based on the first priority and the second priority,

wherein when a value of the second priority is higher than a value of the first priority, the second sequencer circuit outputs a first signal that indicates a start of a second process executed in the second operation, and the first sequencer circuit controls a start timing of a first process executed in the first operation based on the first signal, such that a timing of the first process executed in the first operation is delayed so as to not overlap with a timing of the second process executed in the second operation.

2. The semiconductor memory according to claim 1 ,

wherein the first process comprises a process that increases an amount of current flowing within a word line or bit line associated with the first memory cell array, and

wherein the second process comprises a process that increases an amount of current flowing within a word line or bit line associated with the second memory cell array.

3. The semiconductor memory according to claim 1 ,

wherein the first signal is output based on an amount of current consumption caused by the second process.

4. The semiconductor memory according to claim 1 ,

wherein the first and second circuits set values of the first and second priorities based on an input order of commands respectively provided for the first and second operations to be performed on the first and second planes, an address indicating a selected area in the first and second planes, and a second signal indicating an operating status of each of the first and second planes.

5. The semiconductor memory according to claim 1 , wherein

when the control circuit receives from a controller, a first command that includes an instruction to change a priority of the first operation along with a second command for the first operation,

the control circuit sets a value of the first priority based on the first command.

6. The semiconductor memory according to claim 1 , wherein

when the control circuit receives from a controller, a command that includes an instruction to transmit a value of the first priority of the first operation,

the control circuit transmits the value of the first priority to the controller in response to the command.

7. A memory system comprising:

a controller; and

a semiconductor memory including a first plane of memory cells, a second plane of memory cells, and a control circuit that includes a first circuit configured to store a first priority for a first operation performed on the first plane in response to a first command from the controller, a second circuit configured to store a second priority for a second operation performed on the second plane in response to a second command from the controller, a first sequencer circuit for the first plane, and a second sequencer circuit for the second plane, wherein

the controller is configured to control the first and second operations based on the first priority and the second priority, wherein when a value of the second priority is higher than a value of the first priority, the second sequencer circuit outputs a first signal that indicates a start of a second process executed in the second operation, and the first sequencer circuit controls a start timing of a first process executed in the first operation based on the first signal, such that a timing of the first process executed in the first operation is delayed so as to not overlap with a timing of the second process executed in the second operation.

8. The memory system according to claim 7 ,

wherein the first process comprises a process that increases an amount of current flowing within a word line or bit line associated with the first memory cell array, and

wherein the second process comprises a process that increases an amount of current flowing within a word line or bit line associated with the second memory cell array.

9. The memory system according to claim 7 ,

wherein the first signal is output based on an amount of current consumption caused by the second process.

10. The memory system according to claim 7 ,

wherein the first and second circuits set values of the first and second priorities based on the first and second commands, an address indicating a selected area in the first and second planes, and a second signal indicating an operating status of each of the first and second planes.

11. The memory system according to claim 7 , wherein

when the control circuit receives from the controller, a third command that includes an instruction to change a priority of the first operation along with the first command,

the control circuit sets a value of the first priority based on the third command.

12. The memory system according to claim 7 , wherein

when the control circuit receives from the controller, a third command that includes an instruction to transmit a value of the first priority of the first operation,

the control circuit transmits the value of the first priority to the controller in response to the third command.

13. A method of performing parallel operations in a semiconductor memory including a first plane of memory cells, a second plane of memory cells, and a control circuit that includes a first circuit configured to store a first priority for a first process of a first operation performed on the first plane and a second circuit configured to store a second priority for a second process of a second operation performed on the second plane, said method comprising:

determining that an amount of current consumption by the first and second processes exceeds a threshold; and

when the amount of current consumption by the first and second processes exceeds the threshold, controlling the first and second operations based on the first priority and the second priority, wherein when a value of the second priority is higher than a value of the first priority, a timing of the first process executed in the first operation is delayed so as to not overlap with a timing of the second process executed in the second operation.

14. The method according to claim 13 , further comprising:

setting values of the first and second priorities based on an input order of commands respectively provided for the first and second operations to be performed on the first and second planes, respectively, an address indicating a selected area in the first and second planes, and a second signal indicating an operating status of each of the first and second planes.

15. The method according to claim 13 , further comprising:

setting a value of the first priority based on a first command that includes an instruction to change a priority of the first operation along with a second command for the first operation.

16. The method according to claim 13 , further comprising:

receiving a command that includes an instruction to return a value of the first priority of the first operation, and

returning the value of the first priority in response to the command.

17. The method according to claim 13 , further comprising:

increasing a value of the first priority for the first process after the second process completes.