IP Library Granted Patent US 10,833,096
Granted Patent B2
US 10,833,096 · App. 16/118,583 · Granted Nov 10, 2020

Semiconductor device

Inventors: Ryo Tanaka (Yokkaichi, JP); Hiroyuki Yamasaki (Nagoya, JP); Hideaki Harakawa (Yokkaichi, JP)
Assignee: Toshiba Memory Corporation
H01L27/11582H01L27/1157H01L27/11565H01L29/04H01L29/0649H01L29/1037H01L29/16H01L21/0262H01L21/02532H01L21/02595H01L21/02636H01L21/26513H01L21/31116
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Quick Facts
Patent No.
US 10,833,096
App. No.
16/118,583
Granted
Nov 10, 2020
Kind
B2
Abstract

According to one embodiment, a semiconductor device includes: a first pillar penetrating a first stack and including a first insulator, a first portion of a first semiconductor provided on an upper and an outer side surface of the first insulator, a second insulator provided on an outer side surface of the first portion, and a second portion being provided above the first stack, being coupled to an upper surface of the first portion, and including a lower surface greater than the upper surface of the first portion; an oxide film provided on a side surface of the second portion; and a second pillar penetrating a second stack and including a second semiconductor electrically coupled to the first semiconductor, and a third insulator on an outer side surface of the second semiconductor.

Claims (28)

1. A semiconductor device comprising:

a substrate;

a first stack body which is provided above the substrate and in which a first insulation layer and a first conductive film are alternately stacked;

a first pillar provided to penetrate the first stack body in a direction in which the first insulation layer and the first conductive film are stacked, the first pillar including a first insulator, a first portion of a first semiconductor provided on an upper surface and an outer side surface of the first insulator, a second insulator provided on an outer side surface of the first portion of the first semiconductor, and a second portion of the first semiconductor that is provided above the first stack body, that is coupled to an upper surface of the first portion of the first semiconductor, and that includes a lower surface greater than the upper surface of the first portion of the first semiconductor;

an oxide film provided on a side surface of the second portion of the first semiconductor;

a second stack body which is provided above the second portion of the first semiconductor and the oxide film and in which a second insulation layer and a second conductive film are stacked; and

a second pillar provided to penetrate the second stack body in a direction in which the second insulation layer and the second conductive film are stacked, the second pillar including a second semiconductor electrically coupled to the first semiconductor and a third insulator provided on an outer side surface of the second semiconductor.

2. The device of claim 1 , wherein

an outer periphery of the lower surface of the second portion of the first semiconductor is positioned at a substantially equal distance in width from an outer periphery of the upper surface of the first portion of the first semiconductor.

3. The device of claim 1 , wherein

the second portion of the first semiconductor and the oxide film are provided in a same layer.

4. The device of claim 1 , wherein

the second portion of the first semiconductor has a dome shape.

5. The device of claim 1 , wherein

the second portion of the first semiconductor includes a polysilicon doped with N + -type impurities.

6. The device of claim 1 , wherein

the third insulator includes:

a first oxide provided on an outer side surface of the second semiconductor;

a first nitride provided on an outer side surface of the first oxide; and

a second oxide provided on an outer side surface of the first nitride.

7. The device of claim 1 , wherein

a center of the first pillar and a center of the second pillar are deviated from each other.

8. The device of claim 7 , wherein

a first string, a second string, and a third string are provided on the substrate, each of the first string, the second string, and the third string including the first pillar and the second pillar, and

wherein the second conductive film includes a first portion of the second conductive film that intersects with the second pillar of the first string and the second pillar of the second string, and a second portion of the second conductive film that intersects with the second pillar of the third string and that is electrically decoupled from the first portion of the second conductive film, and

the first pillar of the first string, the first pillar of the second string, and the first pillar of the third string are arranged at a substantially equal distance above the substrate.

9. The device of claim 8 , further comprising:

a fourth insulator formed above the first pillar of the second string and the first pillar of the third string, and configured to electrically decouple the first portion of the second conductive film and the second portion of the second conductive film.

Assignments (4)
CHANGE OF NAME AND ADDRESS Recorded Feb 4, 2022
From: K.K PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 058957/0124 →
CHANGE OF NAME AND ADDRESS Recorded Jan 31, 2022
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 058905/0582 →
MERGER Recorded Jan 31, 2022
From: TOSHIBA MEMORY CORPORATION
To: K.K PANGEA
Reel/Frame 058946/0675 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 31, 2018
From: TANAKA, RYO; YAMASAKI, HIROYUKI; HARAKAWA, HIDEAKI
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 046764/0720 →
Cited By (2)
US 12,550,324 US 12,652,801